The seminal work of Viola and Jones for automatic face detection is widely used in many human–computer interaction and computer vision applications. On analyzing the existing face detection architectures, we observed that integral image calculation, feature computation in cascaded classifier, and recursive scanning of image with sliding window at multiple scales are the major reasons which increase the memory and time complexity of the algorithm. Therefore, in this paper, we have proposed a hardware–software co-design of Viola–Jones face detector for System-on-Chip (SoC). In the proposed architecture, integral image computation and cascaded classifier sub-modules are implemented on the hardware — Programmable Logic FPGA (PL-FPGA), while the image scaling and nonmaximum suppression sub-modules are implemented on the software — Processing System ARM (PS-ARM). Concepts of pipelining, folding, and parallel processing are effectively utilized to produce an optimum design architecture. The proposed architecture has been tested on PYNQ-Z1 board. The implementation results in a processing speed of $95$ fps with PL and PS clocks of $100$$$MHz and $650$$$MHz, respectively, for an image of QVGA resolution. Results analysis demonstrates that the proposed architecture has minimum resource requirement as compared to state-of-the-art implementations, which facilitates and promotes the usage of resource-constrained low-cost ZYNQ SoC for face detection.

Viola 和 Jones 在自动人脸检测方面的开创性工作被广泛应用于许多人机交互和计算机视觉应用中。在分析现有的人脸检测体系结构时，我们发现整体图像计算、级联分类器中的特征计算以及多尺度滑动窗口递归扫描图像是增加算法内存和时间复杂度的主要原因。因此，在本文中，我们提出了一种用于片上系统 (SoC) 的 Viola-Jones 人脸检测器的硬件-软件协同设计。在所提出的架构中，积分图像计算和级联分类器子模块在硬件上实现——可编程逻辑 FPGA (PL-FPGA)，而图像缩放和非极大值抑制子模块是在软件上实现的——Processing System ARM (PS-ARM)。有效地利用流水线、折叠和并行处理的概念来产生最佳设计架构。所提出的架构已在 PYNQ-Z1 板上进行了测试。实施结果的处理速度为$9\mathrm{5个}$具有 PL 和 PS 时钟的 fps$\mathrm{1个}00$$$兆赫和$\mathrm{6个}\mathrm{5个}0$$$MHz，分别用于 QVGA 分辨率的图像。结果分析表明，与最先进的实现相比，所提出的架构具有最低的资源需求，这促进并促进了资源受限的低成本 ZYNQ SoC 在人脸检测中的使用。