This study applies artificial neural networks (ANNs) to increase stuck-at and delay fault coverage of logic built-in self-test (LBIST) through test point insertion (TPI). Increasing TPI quality is essential for modern logic circuits, but the computational requirements of current TPI heuristics scale unfavorably against increasing circuit complexity, and heuristics that evaluate a TPs quality can mask the effects of delay-causing defects that are common in modern technologies. Previous studies show ANNs giving substantial benefits to a wide array of electronic design automation (EDA) problems, including design-for-test (DFT), but their application to various DFT problems is in its infancy. This study demonstrates how to train an ANN to evaluate test points (TPs) and demonstrates a substantial decrease in TPI computation time compared to existing heuristics while delivering comparable stuck-at and delay fault coverage.

本研究应用人工神经网络 (ANN) 通过测试点插入 (TPI) 增加逻辑内置自测 (LBIST) 的固定和延迟故障覆盖率。提高 TPI 质量对于现代逻辑电路至关重要，但当前 TPI 启发式的计算要求不利于电路复杂性的增加，并且评估 TP 质量的启发式可以掩盖现代技术中常见的导致延迟的缺陷的影响。先前的研究表明，人工神经网络对包括测试设计 (DFT) 在内的各种电子设计自动化 (EDA) 问题有很大的好处，但它们在各种 DFT 问题中的应用还处于起步阶段。