A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input—driven by the analog input and by the reference slope generated by an FPGA output buffer—is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between −0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from −0.72 to 0.78 LSB.

中文翻译：

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基于 FPGA 的 7.4 位 ENOB 600 MS/s 在线校准斜率 ADC，无需外部组件

本文提出了一种无需任何外部有源或无源元件即可在数字现场可编程门阵列 (FPGA) 上完全实现的斜率模数转换器 (ADC)。由模拟输入和 FPGA 输出缓冲器生成的参考斜率驱动的标准 LVDS 差分输入的转换时间中编码的振幅信息由 FPGA 时间数字转换器检索。与 ADC 一起开发了一种新的在线校准算法，以减轻过程、电压和温度变化对其性能的影响。ADC 原型的测量显示模拟输入范围为 0.3 V 至 1.5 V，最低有效位 (LSB) 为 2.6 mV，有效位数 (ENOB) 为 7.4 位，速率为 600 MS/s。