Design space exploration of a configurable, heterogeneous system for a given application with required throughput searches for a combination of cores or softcores with different architectures that can be accommodated within the given ASIC or FPGA area and that achieves the required throughput and optimizes power consumption. For a soft real-time streaming application, modeled as a task graph with internally parallelizable streaming tasks, this requires assigning a core type and quantity and DVFS frequency level to each task, which implies task runtime and energy consumption, and mapping and scheduling the tasks, such that the throughput requirement is met. We tightly integrate such static scheduling for stream processing applications with design space exploration of the best heterogeneous core combination, and solve the resulting combined optimization problem by an integer linear program (ILP). We evaluate our solution for different numbers of core types on synthetic and application-based task graphs, and demonstrate improvements of up to 34.8% for ARM big and LITTLE cores, and 70.5% for 3 different core types.

针对具有所需吞吐量的给定应用程序的可配置异构系统的设计空间探索搜索具有不同架构的内核或软核组合，这些架构可以容纳在给定的 ASIC 或 FPGA 区域内，并实现所需的吞吐量并优化功耗。对于软实时流应用程序，建模为具有内部可并行流任务的任务图，这需要为每个任务分配核心类型和数量以及 DVFS 频率级别，这意味着任务运行时间和能耗，以及映射和调度任务，从而满足吞吐量要求。我们将流处理应用程序的这种静态调度与最佳异构核心组合的设计空间探索紧密集成在一起，并通过整数线性规划 (ILP) 解决由此产生的组合优化问题。我们在综合和基于应用程序的任务图上针对不同数量的核心类型评估我们的解决方案，并展示了 ARM 大核心和小核心高达 34.8% 的改进，以及 3 种不同核心类型的 70.5% 的改进。