Power semiconductor chips are parallelly packed in modules to achieve a specific current capacity and power level. An inhomogeneous degradation of the solder layer makes the junction temperature between chips unevenly distributed in multichip modules. The real matters of the junction temperature represented by the terminal electrical characteristics are not known when a junction temperature difference occurs in the internal chip of a multichip IGBT module. This paper analyzes the electrothermal coupling characteristics among the chips in multichip modules and establishes a mathematical model of the electrothermal relationship. To accurately control the different temperature distributions and uneven aging conditions of paralleled chips, two power modules or two discrete devices packaged in a TO-247 are connected in parallel to simulate a multichip power module. The correctness of the proposed electrothermal model and the feasibility of simulating multichip modules are verified through experiments. The findings indicate that the temperature evaluated by the threshold voltage approaches the maximum temperature of the chips inside the module. The junction temperature evaluated by the maximum change rate of the collector–emitter voltage and that of the collector current approach are used to obtain the average temperature.

功率半导体芯片并行封装在模块中，以实现特定的电流容量和功率水平。焊料层的不均匀退化使得芯片之间的结温在多芯片模块中分布不均匀。当多芯片IGBT模块的内部芯片发生结温差时，终端电气特性所代表的结温的真实情况是未知的。分析了多芯片模块中芯片间的电热耦合特性，建立了电热关系的数学模型。为了准确控制并联芯片的不同温度分布和不均匀时效条件，两个电源模块或两个封装在 TO-247 中的分立器件并联连接以模拟多芯片电源模块。通过实验验证了所提出的电热模型的正确性和仿真多芯片模块的可行性。研究结果表明，阈值电压评估的温度接近模块内部芯片的最高温度。通过集电极-发射极电压的最大变化率和集电极电流的方法评估的结温被用来获得平均温度。研究结果表明，阈值电压评估的温度接近模块内部芯片的最高温度。通过集电极-发射极电压的最大变化率和集电极电流的方法评估的结温被用来获得平均温度。研究结果表明，阈值电压评估的温度接近模块内部芯片的最高温度。通过集电极-发射极电压的最大变化率和集电极电流的方法评估的结温被用来获得平均温度。