Although several synthesis methods for asynchronous circuits exist, only limited test methodologies have been developed. This paper presents a built-in self-test (BIST) architecture for Multi-Threshold NULL Convention Logic (MTNCL) asynchronous circuits that utilizes an automated, industry-standard tool-based flow. The software procedure for, and hardware components to implement, BIST functionality are explained. To improve testing performance, the MTNCL pipeline is separated into multiple parallel BIST circuits, with standard pipeline components doubling as BIST circuitry to reduce area overhead. Results of this BIST architecture and software performance is explored for three different test cases looking at area impact and effects of varying the number of input patterns and initial seeds. Further refinements to fault exclusions based upon operating principles of MTNCL are developed to better depict actual fault coverage; and additional hardware modifications are proposed to improve controllability and observability to further increase fault coverage.

尽管存在几种异步电路的综合方法，但只开发了有限的测试方法。本文介绍了一种用于多阈值 NULL 约定逻辑 (MTNCL) 异步电路的内置自测试 (BI​​ST) 架构，该架构利用基于自动化、行业标准工具的流程。解释了实现 BIST 功能的软件过程和硬件组件。为了提高测试性能，MTNCL 流水线被分成多个并行 BIST 电路，标准流水线组件兼作 BIST 电路以减少面积开销。该 BIST 架构和软件性能的结果针对三个不同的测试用例进行了探索，研究了不同输入模式和初始种子数量的区域影响和影响。基于 MTNCL 的操作原则对故障排除进行了进一步的改进，以更好地描述实际的故障覆盖率；并提出了额外的硬件修改，以提高可控性和可观察性，以进一步增加故障覆盖率。