Sample rate conversion is an essential scheme used in almost every radio design. Supporting sampling rates higher than the clock rates require parallel processing. In this paper, we propose an algorithm for a sample rate converter (SRC) with multiple parallel output phases so that the conversion ratio can be a fixed rational number. Due to the structure of the proposed algorithm, it is suitable for embedded platforms which are restricted by their clock frequency but require very high sample rates. A dual phase output variant of the proposed algorithm is simulated with a 400 MHz input signal to perform a 15/8 conversion. The test and verification of the SRC algorithm is presented with the aid of a design example. A VLSI architecture of the dual phase output SRC is implemented on a Virtex-7 field-programmable gate array (FPGA) and results are presented.

采样率转换是几乎所有无线电设计中使用的基本方案。支持高于时钟速率的采样率需要并行处理。在本文中，我们提出了一种用于具有多个并行输出相位的采样率转换器 (SRC) 的算法，以便转换比可以是一个固定的有理数。由于所提出算法的结构，它适用于受时钟频率限制但需要非常高采样率的嵌入式平台。所提出算法的双相输出变体用 400 MHz 输入信号进行仿真，以执行 15/8 转换。借助设计实例对SRC算法进行了测试和验证。