This article presents a new paradigm for analog placement, which further incorporates poles in addition to the considerations of symmetry island and monotonic current flow while minimizing wire crossings. The nodes along the signal paths in an analog circuit contribute to the poles, and the parasitics on these dominant poles can significantly limit the circuit performance. Although the monotonic placement methods introduced in the previous works can generate simpler routing topologies, the unawareness of poles, especially the dominant and the first non-dominant poles and wire crossings among critical nets, may increase wire load and performance degradation. This article proposes a pole-aware analog layout synthesis methodology to minimize the total wire load and wire crossings while satisfying different symmetry and topological routing constraints. Using a strong-connectivity approach to the group Steiner problem, the presented method for automatic selection of port locations can help reduce total wirelength, increase routing flexibility, and minimize total wire crossings. Experimental results show that the proposed approach results in better solution quality in circuit performance compared with other recent works.

中文翻译：

---

考虑单调电流和导线交叉的极点感知模拟布局综合

本文介绍了一种新的模拟布局范例，除了考虑对称岛和单调电流外，还进一步纳入了极点，同时最大限度地减少了导线交叉。模拟电路中信号路径上的节点对极点有贡献，而这些主要极点上的寄生效应会显着限制电路性能。尽管之前工作中引入的单调布局方法可以生成更简单的布线拓扑，但对极点的不了解，尤其是关键网络中的主要和第一个非主要极点和导线交叉，可能会增加导线负载和性能下降。本文提出了一种极点感知模拟布局综合方法，以最大限度地减少总线负载和线交叉，同时满足不同的对称性和拓扑布线约束。使用强连通性方法解决组斯坦纳问题，所提出的自动选择端口位置的方法可以帮助减少总线长，增加布线灵活性，并最大限度地减少总线交叉。实验结果表明，与其他最近的工作相比，所提出的方法在电路性能方面产生了更好的解决方案质量。