In-memory computing is becoming a popular architecture for deep-learning hardware accelerators recently due to its highly parallel computing, low power, and low area cost. However, in-RRAM computing (IRC) suffered from large device variation and numerous nonideal effects in hardware. Although previous approaches including these effects in model training successfully improved variation tolerance, they only considered part of the nonideal effects and relatively simple classification tasks. This paper proposes a joint hardware and software optimization strategy to design a hardware-robust IRC macro for object detection. We lower the cell current by using a low word-line voltage to enable a complete convolution calculation in one operation that minimizes the impact of nonlinear addition. We also implement ternary weight mapping and remove batch normalization for better tolerance against device variation, sense amplifier variation, and IR drop problem. An extra bias is included to overcome the limitation of the current sensing range. The proposed approach has been successfully applied to a complex object detection task with only 3.85% mAP drop, whereas a naive design suffers catastrophic failure under these nonideal effects.

中文翻译：

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用于目标检测的硬件稳健的 RRAM 计算

内存计算由于其高度并行计算、低功耗和低面积成本，最近正成为深度学习硬件加速器的流行架构。然而，in-RRAM 计算 (IRC) 受到设备变化大和硬件中许多非理想效应的影响。尽管先前在模型训练中包含这些效应的方法成功地提高了变异容限，但它们只考虑了部分非理想效应和相对简单的分类任务。本文提出了一种联合硬件和软件优化策略来设计一个硬件鲁棒的 IRC 宏来进行目标检测。我们通过使用低字线电压来降低单元电流，以便在一个操作中实现完整的卷积计算，从而最大限度地减少非线性加法的影响。我们还实现了三元权重映射并删除了批量归一化，以更好地容忍设备变化、感应放大器变化和 IR 压降问题。包含一个额外的偏置以克服电流感应范围的限制。所提出的方法已成功应用于复杂的目标检测任务，只有 3.85% 的 mAP 下降，而幼稚的设计在这些非理想效应下会遭受灾难性的失败。