This work presents a 4 kb 8T-SRAM computation-in-memory (CIM) macro based on hybrid computation using digital in-memory-array computing (DIMAC) and phase-domain near-memory-array computing (PNMAC). By employing multiple local dual-column arrays (LDCAs), bit-wise multiplications are computed digitally in memory with high energy efficiency and throughput. The PNMAC performs the summation and accumulation in parallel with a high dynamic range by using a proposed steering-DAC-based differential current-controlled-oscillator (DCCO). After the phase-domain accumulation is completed, only a one-time digital conversion needs to be performed using a phase quantizer with negligible phase-to-digital conversion overhead. Moreover, by effectively reusing the steered current to accumulate the multiplication results fed from the DIMAC, the power consumption of the PNMAC can be greatly reduced. The macro fabricated in a 65 nm process achieves 22.4TOPS/W peak energy efficiency and $19.03~\mu \text{W}$ power consumption with a 59.8% zero-skipping rate, which is $96.05\times $ lower than state of the art.

中文翻译：

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使用电流重用差分 CCO 的基于 SRAM 的混合内存计算宏

这项工作提出了一个 4 kb 8T-SRAM 内存计算 (CIM) 宏，该宏基于使用数字内存阵列计算 (DIMAC) 和相域近内存阵列计算 (PNMAC) 的混合计算。通过采用多个局部双列阵列 (LDCA)，可在内存中以高能效和高吞吐量对位乘法进行数字计算。PNMAC 通过使用建议的基于转向 DAC 的差分电流控制振荡器 (DCCO) 以高动态范围并行执行求和和累加。相域累加完成后，只需使用相位量化器进行一次数字转换，相数转换开销可忽略不计。此外，通过有效地重用转向电流来累积从 DIMAC 馈送的乘法结果，PNMAC的功耗可以大大降低。采用 65 nm 工艺制造的宏实现了 22.4TOPS/W 的峰值能效和 $19.03~\mu \text{W}$功耗与 59.8% 的零跳跃率，这是 $96.05\次 $低于最先进的水平。