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A 31-Tap Reconfigurable Analog FIR Filter Using Heterogeneously Integrated Polystrata Delay-Lines
IEEE Microwave and Wireless Components Letters ( IF 3 ) Pub Date : 2022-05-10 , DOI: 10.1109/lmwc.2022.3168505
Eric Wagner 1 , Tim LaRocca 1 , Mark Verderber 2 , Carlos Rezende 3 , Peter May 3
Affiliation  

This letter presents a 31-tap analog finite impulse response (FIR) filter capable of synthesizing bandpass, bandstop, and multinull filter responses with continuous center frequency and bandwidth tuning from less than 1 to 20 GHz. The FIR filter delay-lines are realized using Polystrata 3-D air-metal-dielectric technology and are heterogeneously integrated directly on top of a CMOS die using 100- $\mu \text{m}$ -diameter Sn63Pb37 solder bumps. The CMOS chip contains 7-bit programmable weighting circuits at each delay-line tap to allow synthesis of arbitrary frequency responses limited only by the $Q$ -factor of a 31-tap FIR filter and dynamic range of the weighting elements. The final assembly is 5.04 $\times $ 3.85 $\times $ 3.64 mm3, consumes 200–350 mA from a 1.8-V supply, and shows good repeatability between measured samples.

中文翻译:

使用异构集成多层延迟线的 31 抽头可重构模拟 FIR 滤波器

这封信介绍了一个 31 抽头模拟有限脉冲响应 (FIR) 滤波器,它能够合成带通、带阻和多零点滤波器响应,具有连续的中心频率和从小于 1 到 20 GHz 的带宽调谐。FIR 滤波器延迟线使用 Polystrata 3-D 空气-金属-电介质技术实现,并使用 100- $\mu \text{m}$-直径 Sn63Pb37 焊料凸点。CMOS 芯片在每个延迟线抽头处包含 7 位可编程加权电路,以允许合成仅受 $Q$- 31 抽头 FIR 滤波器的因子和加权元件的动态范围。最终组装是 5.04 $\次$3.85 $\次$3.64 mm 3,在 1.8 V 电源下消耗 200–350 mA,并且在测量样品之间显示出良好的可重复性。
更新日期:2022-05-10
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