In this work, the impact of a large lumped resistor connected to the back-gate (B-G) of an fully depleted silicon-on-insulator (FD-SOI) transistor is studied. A related transition in the frequency responses of output conductance and capacitance is evidenced experimentally by $S$ -parameters measurements in a large frequency range up to 40 GHz. However, present compact model does not correctly reproduce the B-G/substrate network behavior. This calls for a model accounting for both n-well and substrate networks. A small-signal equivalent circuit including distributed elements is thus proposed and compared with experimental results.

中文翻译：

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背栅集总电阻对 FD-SOI MOSFET 交流特性的影响

在这项工作中，研究了连接到完全耗尽绝缘体上硅 (FD-SOI) 晶体管的背栅 (BG) 的大型集总电阻器的影响。输出电导和电容的频率响应的相关转变由实验证明 $新元- 在高达 40 GHz 的大频率范围内进行参数测量。然而，目前的紧凑模型不能正确再现 BG/基板网络行为。这需要一个同时考虑 n 阱和衬底网络的模型。因此提出了一种包括分布式元件的小信号等效电路，并与实验结果进行了比较。