This article presents a ring oscillator (RO)-based all-digital phase-locked loop (ADPLL) that is implemented with a high-gain analog closed loop for supply noise compensation (ACSC). The ACSC not only allows high-frequency oscillation of the RO but also is robust over process, voltage, and temperature (PVT) variations thanks to its replica-based configuration. Moreover, a comprehensive analysis of the noise contribution of the ACSC is conducted for the ADPLL to retain its low-jitter output. Implemented in 40-nm CMOS technology, the ADPLL, with a 1.1-V supply, achieves an rms jitter of 289 fs at 8 GHz without any injected supply noise. Under a 20- $\text{m}\textrm {V}_{\textrm {rms}}$ white supply noise, the ADPLL gives rms jitters of 8.7 and 0.63 ps at 8 GHz when the ACSC is disabled and enabled, respectively. The overall power consumption and the area of the presented ADPLL are 9.48 mW and 0.055 $\textrm {mm} {^{\mathrm{ 2}}}$ , respectively.

中文翻译：

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一种基于低抖动 8GHz RO 的 ADPLL，具有用于电源噪声补偿的 PVT 稳健的基于副本的模拟闭环

本文介绍了一种基于环形振荡器 (RO) 的全数字锁相环 (ADPLL)，它通过用于电源噪声补偿 (ACSC) 的高增益模拟闭环实现。ACSC 不仅允许 RO 的高频振荡，而且由于其基于副本的配置，它在工艺、电压和温度 (PVT) 变化方面具有稳健性。此外，对 ACSC 的噪声贡献进行了综合分析，以使 ADPLL 保持其低抖动输出。ADPLL 采用 40-nm CMOS 技术实现，采用 1.1-V 电源，在 8 GHz 时实现了 289 fs 的 rms 抖动，没有任何注入的电源噪声。20岁以下 $\text{m}\textrm {V}_{\textrm {rms}}$当 ACSC 被禁用和启用时，ADPLL 在 8 GHz 时分别提供 8.7 和 0.63 ps 的 rms 抖动。所展示的 ADPLL 的总功耗和面积分别为 9.48 mW 和 0.055 $\textrm {mm} {^{\mathrm{ 2}}}$， 分别。