A time-interleaved duobinary encoding scheme for the low-power high-bandwidth memory (HBM) I/O interface is proposed with a 65-nm CMOS process. To reduce power consumption in HBM I/O using multiple through-silicon via (TSV) I/Os, a transmitter (TX) that performs duobinary signaling with a voltage-mode driver is proposed. A small area encoder is implemented to generate duobinary output and an edge-boosted pre-driver is proposed to improve the slew rate and the robustness against the process, voltage, and temperature (PVT) variations of the duobinary voltage-mode driver. To convert the duobinary signal into a non-return-to-zero (NRZ) signal, a one-tap decision feedback equalizer (DFE) is used at the receiver (RX). NRZ signal conversion is proposed using one reference voltage and one PMOS switch to reduce the hardware complexity caused by additional reference voltages. An eight-stacked TSV is emulated in the 65-nm CMOS process, and the emulated capacitance of each stack is 100 fF. The energy efficiency of the proposed transceiver chip is 0.373 pJ/b/pF with a 2⁷ – 1 pseudorandom binary sequence at 5 Gb/s.

中文翻译：

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用于 3-D 堆叠 IC 的 5 Gb/s 时间交错电压模式双二进制编码方案

提出了一种用于低功耗高带宽存储器 (HBM) I/O 接口的时间交错双二进制编码方案，采用 65-nm CMOS 工艺。为了使用多个硅通孔 (TSV) I/O 降低 HBM I/O 的功耗，提出了一种使用电压模式驱动器执行双二进制信号的发送器 (TX)。实现了一个小区域编码器来生成双二进制输出，并提出了一个边沿增强预驱动器来提高双二进制电压模式驱动器的压摆率和对过程、电压和温度 (PVT) 变化的鲁棒性。为了将双二进制信号转换为非归零 (NRZ) 信号，在接收器 (RX) 处使用一抽头判决反馈均衡器 (DFE)。NRZ 信号转换建议使用一个参考电压和一个 PMOS 开关，以降低额外参考电压带来的硬件复杂度。在 65-nm CMOS 工艺中模拟了一个八叠 TSV，每个叠层的模拟电容为 100 fF。所提出的收发器芯片的能效为 0.373 pJ/b/pF，2⁷ – 1 个 5 Gb/s 的伪随机二进制序列。