A 20-GHz fractional- ${N}$ analog phase-locked loop (PLL) leveraging a novel high-speed charge pump (CP) and an on-chip frequency reference is demonstrated. An on-chip fully integrable 2.5-GHz frequency reference using Texas Instrument’s indigenous bulk acoustic wave (BAW) resonator is demonstrated. The low noise high-frequency reference allows for significant lowering of the division modulus leading to enhanced suppression of CP, phase-frequency detector (PFD), and loop-filter (LF) noise. A low noise class-C transformer-coupled voltage-controlled oscillator (VCO) further allows for excellent jitter performance over wide integration bandwidths (BWs) while still working with a nominally low PLL loop BW. Capability is built into the design to characterize the PLL with either BAW or external reference. The design is implemented and fabricated in the GlobalFoundries 22-nm fully depleted silicon on insulator (FD-SOI) process. The class-C VCO is measured to be centered at $\sim $ 19.7 GHz with 16% tuning range (TR) while maintaining a flat $\vert {\rm FOM}\vert \sim $ 188 dBc/Hz (10-MHz offset) over the entire TR. The PLL measures an excellent jitter and $\vert {\rm FOM}_{j}\vert $ of 65/92 fs and $\sim $ 249/245 dB in integer/fractional modes, respectively.

中文翻译：

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具有基于 BAW 谐振器的片上 2.5 GHz 基准的低于 100 Fs RMSjitter 20 GHz 小数 N 模拟 PLL

一个 20-GHz 小数 ${N}$演示了利用新型高速电荷泵 (CP) 和片上频率基准的模拟锁相环 (PLL)。演示了使用德州仪器 (TI) 的本地体声波 (BAW) 谐振器的片上完全可集成的 2.5 GHz 频率基准。低噪声高频参考可显着降低分频模数，从而增强对 CP、相位频率检测器 (PFD) 和环路滤波器 (LF) 噪声的抑制。低噪声 C 类变压器耦合压控振荡器 (VCO) 进一步允许在宽集成带宽 (BW) 上实现出色的抖动性能，同时仍可使用标称低的 PLL 环路带宽。设计中内置了使用 BAW 或外部参考来表征 PLL 的能力。该设计在 GlobalFoundries 22 纳米完全耗尽绝缘体上硅 (FD-SOI) 工艺中实施和制造。C类VCO被测量为集中在 $\sim $ 19.7 GHz，具有 16% 的调谐范围 (TR)，同时保持平坦 $\vert {\rm FOM}\vert \sim $ 在整个 TR 上为 188 dBc/Hz（10-MHz 偏移）。PLL 测量出色的抖动和 $\vert {\rm FOM}_{j}\vert $65/92 fs 和 $\sim $ 在整数/小数模式下分别为 249/245 dB。