We review the design trade-offs that exist in CMOS inverter-based shunt-feedback transimpedance amplifier (SF-TIA) when optimizing for energy efficiency. We analyze the performance of series and shunt inductive peaking techniques for bandwidth enhancement and identify the most effective one for low-power CMOS TIAs. As a design example, we present a 128-Gb/s single-ended linear transimpedance amplifier (TIA) intended for use in receivers for 400-G Ethernet optical modules and co-packaged optics. The inverter-based SF-TIA is implemented in a 22-nm fin field-effect transistor (FinFET) CMOS technology, supporting a data rate of 128-Gb/s PAM4 with a dc transimpedance gain of $59.3~{\mathrm{ dB}}{\cdot }\Omega $ while dissipating only 11.2 mW of power from a 0.8-V supply. It achieves a 3-dB transimpedance bandwidth of 45.5 GHz with a total integrated input referred noise current of $2.7~\mu \text{A}_{\text{rms}}$ . These results improve upon the state-of-the-art BiCMOS/CMOS linear TIAs, demonstrating the potential for building highly integrated, low-cost, high-sensitivity 100+G CMOS optical receivers using FinFET CMOS process technology.

中文翻译：

---

128 Gb/s、11.2 mW 单端 PAM4 线性 TIA，在 22 nm FinFET CMOS 中具有 2.7 μArms 输入噪声

在优化能效时，我们回顾了基于 CMOS 反相器的并联反馈跨阻放大器 (SF-TIA) 中存在的设计权衡。我们分析了用于带宽增强的串联和并联电感峰值技术的性能，并确定了对低功耗 CMOS TIA 最有效的技术。作为一个设计示例，我们展示了一个 128-Gb/s 单端线性跨阻放大器 (TIA)，旨在用于 400-G 以太网光学模块和共同封装光学器件的接收器。基于逆变器的 SF-TIA 采用 22-nm 鳍式场效应晶体管 (FinFET) CMOS 技术实现，支持 128-Gb/s PAM4 的数据速率，直流跨阻增益为 $59.3~{\mathrm{ dB}}{\cdot }\Omega $0.8V 电源仅消耗 11.2mW 的功率。它实现了 45.5 GHz 的 3 dB 跨阻带宽，总集成输入参考噪声电流为 $2.7~\mu \text{A}_{\text{rms}}$ . 这些结果改进了最先进的 BiCMOS/CMOS 线性 TIA，展示了使用 FinFET CMOS 工艺技术构建高度集成、低成本、高灵敏度 100+G CMOS 光接收器的潜力。