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A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems
IEEE Journal of Solid-State Circuits ( IF 5.4 ) Pub Date : 2022-01-31 , DOI: 10.1109/jssc.2021.3138797
Takashi Toi 1 , Junji Wadatsumi 1 , Hiroyuki Kobayashi 1 , Yutaka Shimizu 1 , Yuji Satoh 1 , Makoto Morimoto 1 , Rui Ito 1 , Mitsuyuki Ashida 1 , Yuta Tsubouchi 1 , Mai Nozawa 1 , Go Urakawa 1 , Jun Deguchi 2 , Ryuichi Fujimoto 1
Affiliation  

This article presents a pulse-amplitude modulation (PAM)-4-based 25.6-Gb/s serial interface for high-bandwidth (BW) and large-capacity storage systems consisting of NAND flash memory. A conventional interface with multi-drop bus topology between the NAND flash memories and their controller has an inevitable tradeoff between BW and capacity if we assume a reasonable PCB design in which the numbers of pins and wires near the NAND controller is limited. Although a daisy-chain-based interface can resolve this tradeoff, it requires the additional overheads of bridge chips and procedures for distinguishing between bridge chips. In order to address these challenges, this article presents three key techniques: 1) ring topology; 2) PAM-4-based four-channel multiplexing; and 3) cascaded clock and data recovery (CDR) circuits with phase-error-dependent bang-bang phase detector (PED-BBPD). The fabricated transceiver for the proposed interface using a 28-nm CMOS process achieves energy efficiency of 3.69 pJ/b at 25.6-Gb/s PRBS31 with a bit error rate (BER) of less than $10^{-15}$ through a short channel with 1.84-dB loss. The proposed interface mitigates the overhead of the bridge chips with higher data rate than previous works, and it can achieve a state-of-the-art figure of merit of 1.80 PKG Gb/s/mW, defined as “No. of NAND packages (PKGs) $\times $ data rate/power consumption,” with a controller and four bridge chips.

中文翻译:

采用基于 PAM-4 的四通道多路复用和级联时钟和数据恢复电路的 25.6-Gb/s 接口,用于高带宽和大容量存储系统的环形拓扑

本文介绍了一种基于脉冲幅度调制 (PAM)-4 的 25.6-Gb/s 串行接口,适用于由 NAND 闪存组成的高带宽 (BW) 和大容量存储系统。如果我们假设一个合理的 PCB 设计,其中 NAND 控制器附近的引脚和电线的数量是有限的,那么在 NAND 闪存及其控制器之间具有多点总线拓扑的传统接口不可避免地会在 BW 和容量之间进行权衡。尽管基于菊花链的接口可以解决这种折衷,但它需要桥接芯片的额外开销和区分桥接芯片的程序。为了应对这些挑战,本文提出了三个关键技术:1)环形拓扑;2)基于PAM-4的四通道复用;3) 级联时钟和数据恢复 (CDR) 电路,具有相位误差相关的 bang-bang 相位检测器 (PED-BBPD)。使用 28-nm CMOS 工艺为提议的接口制造的收发器在 25.6-Gb/s PRBS31 下实现了 3.69 pJ/b 的能效,误码率 (BER) 低于 $10^{-15}$通过具有 1.84-dB 损耗的短通道。所提出的接口以比以前的工作更高的数据速率减轻了桥接芯片的开销,并且它可以实现 1.80 PKG Gb/s/mW 的最先进的品质因数,定义为“No. NAND 封装 (PKG) $\次$数据速率/功耗”,带有一个控制器和四个桥接芯片。
更新日期:2022-01-31
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