As the feature size of integrated circuit decreases, semiconductor devices become more susceptible to Single-Event-Upset (SEU) effect. This paper proposes a radiation hardened latch for Triple-Node-Upset (TNU) tolerance, which can block any triple node upset. Compared with previous radiation hardened TNU Tolerant (TNUT) latches, the proposed Low power-consumption TNUT (LTNUT) latch has the lowest power consumption. When compared with TNU Hardened Latch (TNUHL), TNUT Latch, TNU Completely Tolerant latch (TNUCT), Single-event Multiple-Node Upset Tolerant latch (SMNUT), TNU self-Recoverable Latch (TNURL), Low Cost and TNU-self-Recoverable Latch (LCTNURL) and Quadruple Dual Interlocked Storage Cell (Quadruple-DICE), the proposed LTNUT latch achieves reduction in power consumption by 30.77%, 17.11%, 40%, 20.25%, 20.25%, 27.59% and 64%, respectively. The proposed LTNUT latch achieves reduction in delay by 94.98%, 98.33%, 54.19%, 70.63% and 66.59% when compared with TNUHL, TNUT Latch, SMNUT, TNURL, LCTNURL, respectively, and introduces rise in delay by 3.38% and 5.52%, respectively, when compared with TNUCT and Quadruple-DICE. The proposed LTNUT latch has the lowest power consumption and second smallest delay. The proposed latch is not severely sensitive to temperature and voltage variations.

随着集成电路特征尺寸的减小，半导体器件变得更容易受到单事件翻转 (SEU) 效应的影响。本文提出了一种针对三节点翻转 (TNU) 容差的抗辐射锁存器，它可以阻止任何三节点翻转。与以前的抗辐射 TNU 耐受 (TNUT) 锁存器相比，所提出的低功耗 TNUT (LTNUT) 锁存器具有最低的功耗。与 TNU Hardened Latch (TNUHL)、TNUT Latch、TNU Completely Tolerant Latch (TNUCT)、Single-event Multiple-Node Upset Tolerant Latch (SMNUT)、TNU self-Recoverable Latch (TNURL)、低成本和 TNU-self-可恢复锁存器 (LCTNURL) 和四重双互锁存储单元 (Quadruple-DICE)，提出的 LTNUT 锁存器分别实现了 30.77%、17.11%、40%、20.25%、20.25%、27.59% 和 64% 的功耗降低。与 TNUHL、TNUT Latch、SMNUT、TNURL、LCTNURL 相比，提出的 LTNUT 锁存器分别实现了 94.98%、98.33%、54.19%、70.63% 和 66.59% 的延迟减少，并且延迟增加了 3.38% 和 5.52% ，分别与 TNUCT 和 Quadruple-DICE 相比。建议的 LTNUT 锁存器具有最低的功耗和第二小的延迟。所提出的锁存器对温度和电压变化不是很敏感。