Along with the advancement of technology, Negative bias temperature instability (NBTI) has now been considered a severe reliability threat in modern processors causing the device to deteriorate over time. SRAM-based architectures within the memory array are very much prone to the NBTI effect. Since SRAM cells are composed of cross-coupled inverters, one of the PMOS transistors will always be under constant stress and heavily degraded by NBTI, resulting in an increase in threshold voltage and degradation of SNM and performance of SRAM. Similarly, as one the PMOS transistor is always ON, so there will be a leakage power from \(V_{DD}\) to the ground. In this paper, we have proposed a power gated SRAM architecture to reduce the NBTI effect and standby leakage power of a \(4 \times 4\) SRAM array. The proposed gated logic is introduced during the hold state of the SRAM operation. So both the PMOS of the SRAM cell will be OFF during this period and will get sufficient time to relax from NBTI stress. The simulation result shows using our proposed approach overall, 30.41% NBTI-related \(V_{th}\) degradation can be saved and considering only the standby mode, 96.24% NBTI-related degradation can be minimized compared to the conventional SRAM design. Moreover, 79.10% leakage power can be reduced over the conventional design using the proposed approach.

随着技术的进步，负偏置温度不稳定性 (NBTI) 现在已被认为是现代处理器中严重的可靠性威胁，导致设备随着时间的推移而退化。存储器阵列中基于 SRAM 的架构非常容易产生 NBTI 效应。由于 SRAM 单元由交叉耦合的反相器组成，因此其中一个 PMOS 晶体管将始终处于恒定应力下并被 NBTI 严重劣化，导致阈值电压增加，SNM 和 SRAM 性能下降。类似地，作为一个 PMOS 晶体管始终处于开启状态，因此会有一个从\(V_{DD}\)到地的泄漏功率。在本文中，我们提出了一种电源门控 SRAM 架构，以降低\(4\times 4\)的 NBTI 效应和待机泄漏功率。SRAM 阵列。在 SRAM 操作的保持状态期间引入了建议的门控逻辑。因此 SRAM 单元的两个 PMOS 在此期间都将关闭，并且将有足够的时间从 NBTI 应力中放松。仿真结果表明，总体而言，使用我们提出的方法，可以节省 30.41% 与 NBTI 相关的\(V_{th}\)劣化，并且仅考虑待机模式，与传统 SRAM 设计相比，可以最大限度地减少 96.24% 与 NBTI 相关的劣化。此外，使用所提出的方法，可以比传统设计减少 79.10% 的泄漏功率。