Abstract

The results of modeling the processes of masking noise arising from the collection of charge by transistors from the tracks of single ionizing particles with a linear energy transfer (LET) of 60 MeV cm²/mg are presented in a majority element based on the NAND CMOS logic. They were modeled using the 3D TCAD physical models of CMOS transistors according to the design standard of 65 nm bulk technology with the shallow trench isolation of transistor groups. Charge collection from the track leads to the formation of noise pulses. The majority element has an original topological structure, in which the transistors of the output gate 3NAND are inserted one-by-one into the corresponding transistor groups of the two-input 2NAND elements. A feature of the majority element is masking the noise (blocking their transmission to the output) that occurs when the charge is collected from the track after switching the element at the inputs from 0 to 1 and before switching the element at the inputs from 1 to 0. When masking, no noise pulses appear at the output of the majority element.

中文翻译：

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从基于 CMOS NAND 逻辑的多数元件中的单个电离粒子轨道收集电荷时屏蔽噪声脉冲

摘要

^{对由晶体管从具有 60 MeV cm 2}的线性能量转移 (LET) 的单个电离粒子轨道收集电荷产生的噪声掩蔽过程进行建模的结果/mg 以基于 NAND CMOS 逻辑的多数元素呈现。采用 CMOS 晶体管的 3D TCAD 物理模型，根据 65 nm 体技术的设计标准和晶体管组的浅沟槽隔离对它们进行建模。从轨道收集电荷会导致噪声脉冲的形成。多数元件具有原始拓扑结构，其中输出门3NAND的晶体管一个接一个地插入到两个输入2NAND元件的相应晶体管组中。多数元件的一个特点是屏蔽噪声（阻止它们传输到输出），当输入的元件从 0 切换到 1 之后，输入的元件从 1 切换到之前，从轨道收集电荷时会出现这种噪声。 0.掩蔽时，