Due to the exponential increase of transistor leakage currents, especially in the technologies lower than 90nm, the static power consumption has dramatically increased. So, it is regarded as one of the main problems of the CMOS circuits. The spintronic devices, such as magnetic tunnel junction (MTJ), have notable advantages including low-static power consumption, nonvolatility, high endurance, compatibility with the CMOS transistors and the possibility of fabrication in high scales. Hence, the hybrid MTJ/CMOS circuits are considerable options to mitigate the problem of high-static power consumption in CMOS circuits. In this paper, a nonvolatile and low-power hybrid MTJ/CMOS full adder is proposed for implementation of in-memory computing. The drawback of existing full adders is their low-speed and high-power consuming for MTJ switching, which terribly affect the performance of multi-bit adders using these full adders. In this work, a new full adder is designed by eliminating the MTJ and transistor related to the input carry bit and modifying the tree structure of the MTJ network associated with the other inputs. In the proposed full adder, the effect of carry propagation has drastically decreased and its power consumption is also improved.

中文翻译：

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减少进位传播对自旋电子加法器的影响

由于晶体管漏电流呈指数增长，特别是在低于 90 的技术中nm，静态功耗显着增加。因此，它被认为是CMOS电路的主要问题之一。自旋电子器件，例如磁隧道结 (MTJ)，具有显着的优势，包括低静态功耗、非易失性、高耐用性、与 CMOS 晶体管的兼容性以及大规模制造的可能性。因此，混合 MTJ/CMOS 电路是缓解 CMOS 电路中高静态功耗问题的重要选择。本文提出了一种非易失性和低功耗混合 MTJ/CMOS 全加器，用于实现内存计算。现有全加器的缺点是MTJ切换速度低、功耗大，严重影响了使用这些全加器的多位加法器的性能。在这项工作中，通过消除与输入进位位相关的 MTJ 和晶体管并修改与其他输入相关的 MTJ 网络的树形结构，设计了一个新的全加器。在所提出的全加器中，进位传播的影响已大大降低，其功耗也得到了改善。