The crystallographic microstructure between the electroplated Cu fillings and the substrate in a stacked-via structure and its electrical/mechanical characteristics were systematically investigated using a focused ion beam (FIB), electron backscatter diffraction (EBSD), a probe station with an ohmmeter, a quick via pull (QVP) test, and a 3D-optical microscope. A two-stage Cu electrodeposition process with various plating current densities at the early stage (j₁ = 0.3, 0.5, 1.0, or 2.0 A/dm²) and a fixed plating current density at the subsequent stage (j₂ = 2.0 A/dm²) was utilized to fill a daisy-chain blind-hole (BH) structure. The Cu crystal coherency between electroplated Cu fillings and substrate can be significantly improved with the j₁ minimization, which efficiently enhances the electrical/mechanical characteristics of the stacked-via structure. The strong dependence of the Cu crystal coherency on j₁ can be ascribed to a slow discharge rate of Cu ions at a low plating current density, allowing the Cu nuclei to laterally extend and epitaxially grow with a crystalline substrate. Therefore, the Cu crystal modification via j₁ adjustment can greatly promote the packaging reliabilities of a stacked-via structure.

使用聚焦离子束(FIB)、电子背散射衍射 (EBSD)、带有欧姆计的探针台、a快速通过拉力 (QVP) 测试和 3D 光学显微镜。一种两阶段的Cu电沉积工艺，早期电镀电流密度不同（ j ₁  = 0.3、0.5、1.0或2.0 A/dm ²），后续阶段电镀电流密度固定（j ₂  = 2.0 A/分米²) 用于填充菊花链盲孔 (BH) 结构。j ₁最小化可以显着改善电镀Cu填充物和基板之间的Cu晶体相干性，这有效地增强了堆叠通孔结构的电/机械特性。Cu 晶体相干性对j ₁的强烈依赖性可归因于在低电镀电流密度下 Cu 离子的缓慢放电速率，允许 Cu 核横向延伸并与晶体衬底一起外延生长。因此，通过j ₁调整Cu晶体改性可以大大提高堆叠通孔结构的封装可靠性。