This paper comprehensively analyzes desaturation (desat) protection for high voltage (>3.3 kV) silicon carbide (SiC) MOSFETs and especially how to build in noise immunity under high dv/dt . This study establishes a solid foundation for understanding the trade-offs between noise immunity and response speed of desat protection. Two implementations of the desat protection for high voltage SiC MOSFETs are examined, including desat protection based on discrete components and desat protection realized with a gate driver integrated circuit (IC). Both positive dv/dt and negative dv/dt are investigated. Analysis results show that the high dv/dt with long duration caused by high voltage SiC MOSFETs’ switching results in strong noise interference in the desat protection circuitry. The impact of numerous influencing factors is investigated analytically, such as parasitic capacitances, parasitic inductance, damping resistance, and clamping impedance. Under high positive dv/dt , extremely small parasitic capacitances (<0.01 pF) between the drain terminal and protection circuitry could still compromise noise immunity of the desat protection circuitry that has a high-impedance voltage divider. Comprehensive design guidelines are summarized to boost the noise immunity, including circuit design, component selection, and PCB layout. The noise immunity margin under the positive dv/dt is also derived quantitatively to guide the noise immunity improvement. The noise immunity analysis results and noise immunity improvement methods are validated with simulation and experimental results obtained from a phase leg based on 10 kV/20 A SiC MOSFETs.

中文翻译：

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高DV/DT高压SiC MOSFET去饱和保护抗噪声综合分析及改进方法

本文全面分析了高压 (>3.3 kV) 碳化硅 (SiC) MOSFET 的去饱和 (desat) 保护，尤其是在高电压条件下如何构建抗噪能力。 dv/dt。本研究为理解去饱和保护的抗噪性和响应速度之间的权衡奠定了坚实的基础。研究了高压 SiC MOSFET 去饱和保护的两种实现方式，包括基于分立元件的去饱和保护和通过栅极驱动器集成电路 (IC) 实现的去饱和保护。双方积极dv/dt 和负 dv/dt 被调查。分析结果表明，高由高压 SiC MOSFET 的开关引起的持续时间较长的 dv/dt 会在去饱和保护电路中产生强烈的噪声干扰。分析研究了许多影响因素的影响，例如寄生电容、寄生电感、阻尼电阻和钳位阻抗。高正下dv/dt ，漏极端子和保护电路之间的极小寄生电容 (<0.01 pF) 仍可能损害具有高阻抗分压器的去饱和保护电路的抗噪声能力。总结了全面的设计指南以提高抗噪能力，包括电路设计、组件选择和 PCB 布局。正下的抗噪裕度dv/dt 也是定量推导的，以指导噪声抗扰度的提高。通过从基于 10 kV/20 A SiC MOSFET 的相脚获得的仿真和实验结果验证了噪声抗扰度分析结果和噪声抗扰度改进方法。