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Design and Optimization of a Dual-Source Triple Gate FET Using Electrostatically Induced Reconfigurable Property
IETE Technical Review ( IF 2.4 ) Pub Date : 2021-12-22 , DOI: 10.1080/02564602.2021.2012284
Antara Kundu 1 , Priyanka Saha 1 , Subir Kumar Sarkar 1
Affiliation  

Reconfigurable field effect transistors (RFETs) have opened a new avenue of research domain enabling multiple logical computations with the same hardware cost. So far, mostly, the same device capable of switching between n and p-type polarity has been realized as RFET. In this paper, applying multi-gate geometry, the doping is tuned electrostatically to operate the single device either as TFET or in a MOSFET mode depending upon the biases applied. A dual-source triple gate (DS-TG) FET is presented here as RFET with two gates over the source as program gates to switch the source polarity, while the control gate modulates the drain current. Based on the ATLAS simulated data, a high ON current of 10−5A/µm, the lower average subthreshold slope of 52 mV/decade, and improved ION/IOFF ratio of 1012 are recorded with DS-TG TFET owing to its dual-source configuration and enhanced tunneling area. The impact of varying parameters, including channel doping concentration, distance between the source and drain, work function of gate metals, have been investigated on device electrostatics and its reconfigurable property to obtain the optimum device functionality. The performance of the present device is benchmarked against some of the concurrent TFET structures to establish its superiority for future circuit and system-level implementation.



中文翻译:

利用静电感应可重构特性设计和优化双源三栅极 FET

可重构场效应晶体管 (RFET) 开辟了一条新的研究领域途径,能够以相同的硬件成本进行多种逻辑计算。到目前为止,大多数情况下,能够在 n 型和 p 型极性之间切换的同一器件已实现为 RFET。在本文中,应用多栅极几何结构,静电调节掺杂以根据施加的偏置将单个器件作为 TFET 或 MOSFET 模式运行。双源三栅极 (DS-TG) FET 在这里作为 RFET 呈现,在源极上方有两个栅极作为编程栅极来切换源极极性,而控制栅极调制漏极电流。基于 ATLAS 模拟数据,10 −5 A/µm 的高导通电流,52 mV/decade 的较低平均亚阈值斜率,以及改进的 I ON /I由于其双源配置和增强的隧道面积,DS-TG TFET 记录了10 12的关断比。已经研究了不同参数(包括沟道掺杂浓度、源极和漏极之间的距离、栅极金属的功函数)对器件静电及其可重构特性的影响,以获得最佳器件功能。本设备的性能针对一些并发 TFET 结构进行了基准测试,以确定其在未来电路和系统级实施中的优势。

更新日期:2021-12-22
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