A continuous-Time delta–sigma modulator (CT-DSM) excels at high-bandwidth (BW), high-dynamic-range analog-to-digital conversion. However, CT-DSMs suffer from PVT variation, high sensitivity to timing errors, and are restricted in sampling rate. This work proposes a hybrid-loop (HL) DSM architecture to mitigate the disadvantages of CT-DSM while providing similar performance. This work also introduces a bandpass time-interleaved noise-shaping (TINS) successive-approximation (SAR) architecture, which increases the sampling rate of TINS SAR. A prototype HL-DSM with bandpass TINS-SAR quantizer is built in 28-nm CMOS and occupies a die area of 0.09 mm ² . The measured peak SNDR is 67.5 dB for a 100-MHz BW. The total power consumption is 13.4 mW at a sampling rate of 1.6 GS/s. The resulting Schreier FoM of 166.2 dB is comparable to state-of-the-art CT-DSM converters.

中文翻译：

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用于稳健的 100MHz BW 和 69dB DR DSM 的混合环路结构和交错噪声整形量化器

连续时间 delta-sigma 调制器 (CT-DSM) 在高带宽 (BW)、高动态范围模数转换方面表现出色。然而，CT-DSM 存在 PVT 变化、对时序误差的高敏感性以及采样率的限制。这项工作提出了一种混合回路 (HL) DSM 架构，以减轻 CT-DSM 的缺点，同时提供类似的性能。这项工作还引入了带通时间交错噪声整形 (TINS) 逐次逼近 (SAR) 架构，从而提高了 TINS​​ SAR 的采样率。带有带通 TINS​​-SAR 量化器的原型 HL-DSM 内置于 28-nm CMOS 中，占用的芯片面积为 0.09 mm ² . 对于 100 MHz 带宽，测得的峰值 SNDR 为 67.5 dB。总功耗为 13.4 mW，采样率为 1.6 GS/s。由此产生的 166.2 dB 的 Schreier FoM 可与最先进的 CT-DSM 转换器相媲美。