Thin-film transistors based on amorphous oxide semiconductors could be used to create low-cost backplane technology for large flat-panel displays. However, a trade-off between mobility and stability has limited the ability of such devices to replace current polycrystalline silicon technologies. Here we show that the sensitivity of amorphous oxide semiconductors to externally introduced impurities and defects is determined by the location of the conduction-band minimum and the relevant doping ability. Using bilayer-structured thin-film transistors, we identify the exact charge-trapping position under bias stress, which shows that the Fermi-level shift in the active layer can occur via electron donation from carbon-monoxide-related impurities. This mechanism is highly dependent on the location of the conduction-band minimum and explains why carbon-monoxide-related impurities greatly affect the stability of high-mobility indium tin zinc oxide transistors but not that of low-mobility indium gallium zinc oxide transistors. Based on these insights, we develop indium tin zinc oxide transistors with mobilities of 70 cm² (V s)^–1 and low threshold voltage shifts of –0.02 V and 0.12 V under negative- and positive-bias temperature stress, respectively.

基于非晶氧化物半导体的薄膜晶体管可用于为大型平板显示器创建低成本背板技术。然而，迁移率和稳定性之间的权衡限制了此类器件替代当前多晶硅技术的能力。在这里，我们表明非晶氧化物半导体对外部引入的杂质和缺陷的敏感性取决于导带最小值的位置和相关的掺杂能力。使用双层结构的薄膜晶体管，我们确定了偏置应力下的确切电荷俘获位置，这表明有源层中的费米能级位移可以通过来自一氧化碳相关杂质的电子捐赠而发生。这种机制高度依赖于导带最小值的位置，并解释了为什么与一氧化碳相关的杂质会极大地影响高迁移率铟锡锌氧化物晶体管的稳定性，而不会影响低迁移率铟镓锌氧化物晶体管的稳定性。基于这些见解，我们开发了迁移率为 70 cm 的铟锡锌氧化物晶体管^{在负偏压和正偏压温度应力下，分别为2}  (V s) ^–1和 –0.02 V 和 0.12 V 的低阈值电压偏移。