To enable accurate system-level electrostatic discharge (ESD) simulation, this article applies statistical learning to obtain I/O port models of the victim integrated circuits (ICs). A quasi-static I–V model derived using kernel regression can capture the circuit board dependency of the behavior observed at the I/O pin, regardless if there is snapback. The non-parametric kernel model can be reduced to a system-specific parametric model, which has smaller requirements for computing time and memory. In some cases, transient system-level ESD simulation may require the IC model to replicate the dynamic behavior of the nonlinear circuit. A recurrent neural network is demonstrated to be a suitable model in such cases. This article provides a detailed RNN training flow for IC pin modeling, and presents a Verilog-A implementation of the RNN for use with Simulation Program with Integrated Circuit Emphasis (SPICE)-type simulators.

中文翻译：

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用于系统级 ESD 仿真的 IC 模型的统计学习

为了实现准确的系统级静电放电 (ESD) 仿真，本文应用统计学习来获取受害集成电路 (IC) 的 I/O 端口模型。准静态使用内核回归导出的 I-V 模型可以捕获在 I/O 引脚处观察到的行为的电路板依赖性，无论是否有回弹。非参数内核模型可以简化为系统特定的参数模型，对计算时间和内存的要求较小。在某些情况下，瞬态系统级 ESD 仿真可能需要 IC 模型复制非线性电路的动态行为。在这种情况下，循环神经网络被证明是合适的模型。本文提供了用于 IC 引脚建模的详细 RNN 训练流程，并介绍了 RNN 的 Verilog-A 实现，以与具有集成电路强调的仿真程序 (SPICE) 类型的模拟器一起使用。