This article introduces a new architecture for a high-resolution digital pulsewidth modulator (HR-DPWM), which generates multiple output phases, all synchronized and derived out of a single reference source. Constructed through digital standard-cell delay chain and simple combinatorial logic, the module produces PWM signals with configurable on-time, period and time-delay (between phases) with resolution of a single delay element. To minimize the statistical error spread (e.g., jitter error) between phases, a single delay-line is utilized to generate a master time-base while combinatorial logic assigns per-phase independent duty-ratio settings. The resultant module minimizes the time-diversity error between phases, as any uncertainty in the on-time generation is identical between phases. The solution is compact, flexible and scales with the number of phases. Since the entire architecture is realized through standard cells, the solution also scales with fabrication technology and is described by HDL, which translates onto hardware using automated process. The HR-DPWM module has been designed and fabricated on a 0.18 μm 5 V CMOS process, totaling 0.08 mm ² of effective silicon area. Experimental results of a four phase 13-bit HR-DPWM are provided, demonstrating high accuracy and linearity characteristics with time resolution of 200 ps and excellent matching and tracking between all phases.

中文翻译：

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从单个同步源生成的数字多相 PWM 集成模块

本文介绍了高分辨率数字脉宽调制器 (HR-DPWM) 的新架构，该架构可生成多个输出相位，所有输出相位均同步并源自单个参考源。该模块通过数字标准单元延迟链和简单的组合逻辑构建，产生具有可配置导通时间、周期和时间延迟（相位之间）的 PWM 信号，具有单个延迟元件的分辨率。为了最小化相位之间的统计误差传播（例如，抖动误差），使用单个延迟线来生成主时基，而组合逻辑分配每相位独立的占空比设置。由此产生的模块最大限度地减少了相位之间的时间分集误差，因为在相位之间生成导通时间的任何不确定性都是相同的。解决方案很紧凑，灵活并随阶段数而变化。由于整个架构是通过标准单元实现的，因此该解决方案还可以随制造技术进行扩展，并由 HDL 描述，HDL 使用自动化过程转换为硬件。HR-DPWM 模块采用 0.18 μm 5 V CMOS 工艺设计和制造，总厚度为 0.08 mm ²有效硅面积。提供了四相 13 位 HR-DPWM 的实验结果，展示了高精度和线性特性，时间分辨率为 200 ps，所有相位之间具有出色的匹配和跟踪。