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APAS: Application-Specific Accelerators for RLWE-Based Homomorphic Linear Transformations
IEEE Transactions on Information Forensics and Security ( IF 6.8 ) Pub Date : 2021-09-20 , DOI: 10.1109/tifs.2021.3114032
Song Bian , Dur E. Shahwar Kundi , Kazuma Hirozawa , Weiqiang Liu , Takashi Sato

Recently, the application of multi-party secure computing schemes based on homomorphic encryption in the field of machine learning attracts attentions across the research fields. Previous studies have demonstrated that secure protocols adopting packed additive homomorphic encryption (PAHE) schemes based on the ring learning with errors (RLWE) problem exhibit significant practical merits, and are particularly promising in enabling efficient secure inference in machine-learning-as-a-service applications. In this work, we introduce a new technique for performing homomorphic linear transformation (HLT) over PAHE ciphertexts. Using the proposed HLT technique, homomorphic convolutions and inner products can be executed without the use of number theoretic transform and the rotate-and-add algorithms that were proposed in existing works. To maximize the efficiency of the HLT technique, we propose APAS, a hardware-software co-design framework consisting of approximate arithmetic units for the hardware acceleration of HLT. In the experiments, we use actual neural network architectures as benchmarks to show that APAS can improve the computational and communicational efficiency of homomorphic convolution by $8\times $ and $3\times $ , respectively, with an energy reduction of up to $26\times $ as compared to the ASIC implementations of existing methods.

中文翻译:

APAS:用于基于 RLWE 的同态线性变换的特定应用加速器

近年来,基于同态加密的多方安全计算方案在机器学习领域的应用引起了各研究领域的关注。先前的研究表明,采用基于带错误环学习 (RLWE) 问题的打包加性同态加密 (PAHE) 方案的安全协议具有显着的实际优点,并且特别有希望在机器学习中实现高效的安全推理。服务应用程序。在这项工作中,我们介绍了一种对 PAHE 密文执行同态线性变换 (HLT) 的新技术。使用所提出的 HLT 技术,可以在不使用现有工作中提出的数论变换和旋转加法算法的情况下执行同态卷积和内积。为了最大限度地提高 HLT 技术的效率,我们提出了 APAS,一种硬件 - 软件协同设计框架,由用于 HLT 硬件加速的近似算术单元组成。在实验中,我们使用实际的神经网络架构作为基准来证明 APAS 可以通过以下方式提高同态卷积的计算和通信效率 $8\times $ $3\times $ , 分别具有高达 $26\times $ 与现有方法的 ASIC 实现相比。
更新日期:2021-10-06
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