In this work, we present a four-transistor-two-resistor (4T2R) ternary content addressable memory (TCAM) bit cell based on the resistive memory (RRAM), comprising the conventional two-transistor-two-resistor (2T2R) cell with two additional comparison transistors. It can effectively amplify the match-line signal ratio (ML-ratio), lower the leakage current of the match cell ( ${I}_{{\mathrm {MATCH}}}$ ), and suppress the read disturbance. The proposed concept is silicon verified using the 180 nm CMOS technology with transition-metal-oxide (TMO) RRAM integrated at the back-end-of-line (BEOL). It achieves a considerable ML-ratio of 1860 and a low ${I}_{{\mathrm {MATCH}}}$ of 11.15 nA on average. In a typical search operation, it shows a negligible ML drop at the match case and a large ML swing range at the mismatch case. The SPICE simulation results further show it can support a long word-length (WDL) of 256 under a clock rate of 100 MHz for search operations, which demonstrates its promise for highly parallel nonvolatile TCAM.

中文翻译：

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用于高度并行三元内容可寻址存储器的 4T2R RRAM 位单元

在这项工作中，我们提出了一种基于电阻式存储器 (RRAM) 的四晶体管双电阻 (4T2R) 三元内容可寻址存储器 (TCAM) 位单元，包括传统的两晶体管双电阻 (2T2R) 单元和两个额外的比较晶体管。它可以有效地放大匹配线信号比（ML-ratio），降低匹配单元的漏电流（ ${I}_{{\mathrm {MATCH}}}$ )，并抑制读取干扰。提议的概念是使用 180 nm CMOS 技术进行硅验证，并在后端 (BEOL) 集成过渡金属氧化物 (TMO) RRAM。它实现了可观的 1860 ML 比率和低 ${I}_{{\mathrm {MATCH}}}$ 平均为 11.15 nA。在典型的搜索操作中，它显示匹配情况下的 ML 下降可以忽略不计，而失配情况下的 ML 摆动范围很大。SPICE 仿真结果进一步表明，它可以在 100 MHz 的时钟速率下支持 256 的长字长 (WDL) 进行搜索操作，这证明了其对高度并行非易失性 TCAM 的承诺。