Planar-gate 2.3 kV 4H-SiC power MOSFETs were successfully fabricated in a commercial foundry with the gate oxide thickness reduced from 55 to 27 nm for the first time. Results of numerical simulations demonstrate acceptable gate oxide electric field despite the increased blocking voltage. For a gate bias of 15 V, the measured specific ON-resistance ( ${R}_{\mathrm {ON},\text {sp}}$ ) and high-frequency figures-of-merit (FOM[ ${R}_{\mathrm {ON}} \times {C}_{\text {gd}}$ ], FOM[ ${R}_{\mathrm {ON}} \times {Q}_{\text {gd}}$ ]) were improved by a factor of $1.3\times $ by reducing the gate oxide thickness even at the larger blocking voltage. Analytical modeling shows that the channel and accumulation layer resistances are still important contributors even at this larger blocking voltage capability. Operating the 27 nm gate oxide devices with the commonly accepted ON-state gate oxide electric field of 4 MV/cm for reliable operation makes the ${R}_{\mathrm {ON},\text {sp}}$ and FOMs for the 27 nm gate oxide case 10% worse than the 55 nm gate oxide case. However, the reduced gate bias of 11 V for the 27 nm gate oxide case reduces input switching power loss in half from a gate drive perspective. In addition, operation at this gate bias makes the saturation current for the 27 nm gate oxide devices three times smaller than for the conventional devices operating at a gate bias of 20 V, which will proportionally increase short-circuit withstand time.

中文翻译：

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使用减小的栅极氧化物厚度提高 2.3 kV 4H-SiC 平面栅极 MOSFET 的性能

平面栅极 2.3 kV 4H-SiC 功率 MOSFET 在商业代工厂成功制造，栅极氧化层厚度首次从 55 nm 减少到 27 nm。数值模拟的结果表明，尽管增加了阻塞电压，但栅极氧化物电场还是可以接受的。对于 15 V 的栅极偏置，测得的特定导通电阻 ( ${R}_{\mathrm {ON},\text {sp}}$ ) 和高频品质因数 (FOM[ ${R}_{\mathrm {ON}} \times {C}_{\text {gd}}$ ], FOM[ ${R}_{\mathrm {ON}} \times {Q}_{\text {gd}}$ ]) 改进了一个因素 $1.3\times $ 即使在较大的阻断电压下，也可以通过减小栅极氧化层厚度。分析模型表明，即使在这种更大的阻断电压能力下，沟道和累积层电阻仍然是重要的贡献者。以 4 MV/cm 的普遍接受的导通状态栅极氧化物电场操作 27 nm 栅极氧化物器件以实现可靠操作，这使得 ${R}_{\mathrm {ON},\text {sp}}$ 27 nm 栅极氧化物情况的 FOM 比 55 nm 栅极氧化物情况差 10%。然而，从栅极驱动的角度来看，27 nm 栅极氧化物情况下的 11 V 栅极偏压降低了一半的输入开关功率损耗。此外，在此栅极偏压下操作使 27 nm 栅极氧化物器件的饱和电流比在 20 V 栅极偏压下操作的传统器件小三倍，这将成比例地增加短路耐受时间。