This paper describes FPGA implementation of a high-order continuous-time multi-stage noise-shaping (MASH) $\Delta \Sigma $ time-to-digital converter (TDC). The TDC is based on Gated Switched-Ring Oscillator (GSRO) and employs multirating technique to achieve improved performance over conventional $\Delta \Sigma $ TDCs. The proposed TDC has been implemented on an Altera Stratix IV FPGA development board. Dynamic and static tests were performed on the proposed design and experimental results demonstrate that it can perform its function without the need of calibration. The built-in clock circuitries of the FPGA board provides sampling clocks and operating frequencies of the GSROs. This work presents a 52 fs _rms , 89.7 dB dynamic range and 0.18 ps time-resolution at 200 MHz, 800 MHz, 1600 MHz sampling rate at the first, second and third stage, respectively, which demonstrate that the proposed third-order TDC can play an important role in applications such as ADPLLs and range finders in which accuracy and speed are vital.

中文翻译：

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在 40 nm Altera Stratix IV FPGA 上实现的多速率 5 位高阶 52 fsrms Δ∑ 时间数字转换器的设计和分析

本文描述了高阶连续时间多级噪声整形 (MASH) 的 FPGA 实现 $\Delta \Sigma $ 时间数字转换器 (TDC)。TDC 基于门控开关环振荡器 (GSRO)，并采用多级技术来实现比传统技术更高的性能 $\Delta \Sigma $ TDC。建议的 TDC 已在 Altera Stratix IV FPGA 开发板上实现。对所提出的设计进行了动态和静态测试，实验结果表明它可以在不需要校准的情况下执行其功能。FPGA 板的内置时钟电路提供 GSRO 的采样时钟和工作频率。这项工作 分别在第一、第二和第三阶段在 200 MHz、800 MHz、1600 MHz 采样率下呈现 52 fs _rms、89.7 dB 动态范围和 0.18 ps 时间分辨率，这表明所提出的三阶 TDC 可以在精度和速度至关重要的 ADPLL 和测距仪等应用中发挥重要作用。