The forward and inverse DCT has many applications in digital signal processing area, but, due to its high arithmetic complexity, it is necessary to find efficient software implementations or even to find VLSI implementations for them. Existing fast algorithms for IDCT or DCT have a SFG graph that is not very regular and modular and, even more importantly, the topology of the interconnection network is not easy to implement in VLSI due to the so-called retrograde indexing. Due to this problem, there are few pipeline implementations for IDCT and DCT, although pipelining is an efficient engineering solution that allows high speed performance with a reduced hardware complexity and power consumption. In this paper, we present an efficient solution to successfully reformulate the IDCT algorithm with a focus on developing a modular and regular computation structure that can be easily implemented using a pipelined VLSI architecture. Using new restructuring input sequences that can be computed in parallel with the new SFG graph in a pipeline manner, a novel efficient fast algorithm for the computation of inverse discrete cosine transform is presented. The obtained SFG graph has the best structure that can be obtained for IDCT, avoiding the so-called retrograde indexing and being highly regular and modular. Moreover, the obtained SFG graph is scalable, being easy to extend to larger values of N that is a power of 2. It can also be used to obtain a generalization of a radix-2 algorithm for length \(N = p \cdot 2^{m}\), where “p” is a prime number. This algorithm is based on a recursive decomposition of the computation of the inverse DCT that requires a reduced number of arithmetic operations and has a regular and simple computational structure that can be easily implemented in VLSI in a pipeline manner. Its main advantages are its simple, regular and modular computational structure and its high potential to be pipelined so that it can be used to obtain an efficient pipeline VLSI implementation.

正向和逆向 DCT 在数字信号处理领域有很多应用，但由于其算法复杂度高，需要为其寻找高效的软件实现甚至 VLSI 实现。现有的 IDCT 或 DCT 快速算法的 SFG 图不是很规则和模块化，更重要的是，由于所谓的逆行索引，互连网络的拓扑结构在 VLSI 中不容易实现。由于这个问题，IDCT 和 DCT 的流水线实现很少，尽管流水线是一种高效的工程解决方案，可以在降低硬件复杂性和功耗的情况下实现高速性能。在本文中，我们提出了一个有效的解决方案来成功地重新制定 IDCT 算法，重点是开发一个模块化和规则的计算结构，可以使用流水线 VLSI 架构轻松实现。使用可以以流水线方式与新 SFG 图并行计算的新重组输入序列，提出了一种用于计算逆离散余弦变换的新型高效快速算法。得到的SFG图具有IDCT所能得到的最佳结构，避免了所谓的逆行索引，具有高度的规则性和模块化。此外，获得的 SFG 图是可扩展的，很容易扩展到更大的 N 值，即 2 的幂。它还可以用于获得 radix-2 算法的泛化长度 使用可以以流水线方式与新 SFG 图并行计算的新重组输入序列，提出了一种用于计算逆离散余弦变换的新型高效快速算法。得到的SFG图具有IDCT所能得到的最佳结构，避免了所谓的逆行索引，具有高度的规则性和模块化。此外，获得的 SFG 图是可扩展的，很容易扩展到更大的 N 值，即 2 的幂。它还可以用于获得 radix-2 算法的泛化长度 使用可以以流水线方式与新 SFG 图并行计算的新重组输入序列，提出了一种用于计算逆离散余弦变换的新型高效快速算法。得到的SFG图具有IDCT所能得到的最佳结构，避免了所谓的逆行索引，具有高度的规则性和模块化。此外，获得的 SFG 图是可扩展的，很容易扩展到更大的 N 值，即 2 的幂。它还可以用于获得 radix-2 算法的泛化长度\(N = p \cdot 2^{m}\)，其中“ p ”是素数。该算法基于逆 DCT 计算的递归分解，该算法需要减少的算术运算次数，并且具有规则和简单的计算结构，可以以流水线方式在 VLSI 中轻松实现。它的主要优点是其简单、规则和模块化的计算结构，以及流水线化的巨大潜力，因此可以用来获得高效的流水线 VLSI 实现。