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A Novel Method to Control Leakage and Noise in Domino Circuit for Wide Fan-In OR Logic
Journal of Circuits, Systems and Computers ( IF 1.5 ) Pub Date : 2021-09-17 , DOI: 10.1142/s0218126622500554
Ankur Kumar 1 , R. K. Nagaria 1
Affiliation  

This paper proposes a novel method to control leakage and noise in domino circuits for wide fan-in OR logic with low power consumption, low process variation, and higher noise margin under the similar delay condition. In the proposed method, output and dynamic nodes are isolated from the PDN (Pull-Down Network) to improve the noise immunity and reduce switching activity. Further, with the aid of a transistor in the stack, the sub-threshold current is reduced. Thus, the proposed domino is applicable for high-speed and low-power applications in deep sub-micro-range. Simulation results show that the proposed domino improves the noise immunity and figure of merit (FOM) by factors of 1.95 and 2.34, respectively, with respect to the conventional domino with a footer. Along with this improvement, 26% reduction is also observed in power consumption. The entire simulations for all the domino circuits are done at 45-nm CMOS technology by using SPECTRE simulator under the Cadence Virtuoso environment.

中文翻译:

一种控制宽扇入或逻辑多米诺电路中泄漏和噪声的新方法

本文提出了一种控制多米诺电路中的泄漏和噪声的新方法,用于在类似延迟条件下具有低功耗、低工艺变化和更高噪声容限的宽扇入 OR 逻辑。在所提出的方法中,输出和动态节点与 PDN(下拉网络)隔离,以提高抗噪能力并减少开关活动。此外,借助堆叠中的晶体管,降低了亚阈值电流。因此,所提出的多米诺骨牌适用于深亚微米范围内的高速和低功耗应用。仿真结果表明,相对于带有页脚的传统多米诺骨牌,所提出的多米诺骨牌分别提高了 1.95 和 2.34 倍的抗噪性和品质因数 (FOM)。随着这一改进,功耗也降低了 26%。
更新日期:2021-09-17
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