Most of the architectural research on photonic implementations of measurement-based quantum computing (MBQC) has focused on the quantum resources involved in the problem with the implicit assumption that these will provide the main constraints on system scaling. However, the `flying-qubit' architecture of photonic MBQC requires specific timing constraints that need to be met by the classical control system. This classical control includes, for example: the amplification of the signals from single-photon detectors to voltage levels compatible with digital systems; the implementation of a control system which converts measurement outcomes into basis settings for measuring subsequent cluster qubits, in accordance with the quantum algorithm being implemented; and the digital-to-analog converter (DAC) and amplifier systems required to set these measurement bases using a fast phase modulator. In this paper, we analyze the digital system needed to implement arbitrary one-qubit rotations and controlled-NOT (CNOT) gates in discrete-variable photonic MBQC, in the presence of an ideal cluster state generator, with the main aim of understanding the timing constraints imposed by the digital logic on the analog system and quantum hardware. We use static timing analysis of a Xilinx FPGA (7 series) to provide a practical upper bound on the speed at which the adaptive measurement processing can be performed, in turn constraining the photonic clock rate of the system. Our work points to the importance of co-designing the classical control system in tandem with the quantum system in order to meet the challenging specifications of a photonic quantum computer.

中文翻译：

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经典数字控制系统对基于测量的量子计算的光子实现施加的时序约束

大多数关于基于测量的量子计算 (MBQC) 的光子实现的架构研究都集中在问题中涉及的量子资源上，并隐含假设这些资源将提供对系统扩展的主要约束。然而，光子 MBQC 的“飞行量子比特”架构需要特定的时序约束，而经典控制系统需要满足这些约束。例如，这种经典控制包括：将来自单光子探测器的信号放大到与数字系统兼容的电压水平；根据正在实施的量子算法，实施控制系统，将测量结果转换为用于测量后续集群量子位的基础设置；以及使用快速相位调制器设置这些测量基准所需的数模转换器 (DAC) 和放大器系统。在本文中，我们分析了在存在理想集群状态生成器的情况下，在离散可变光子 MBQC 中实现任意一量子比特旋转和受控非（CNOT）门所需的数字系统，主要目的是了解时序数字逻辑对模拟系统和量子硬件施加的约束。我们使用 Xilinx FPGA（7 系列）的静态时序分析来提供执行自适应测量处理速度的实用上限，进而限制系统的光子时钟速率。