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Ultra Steep Ge-Source Dopingless Tunnelling Field Effect Transistor with Enhanced Drive Current: DC to Linearity Characteristics Analysis
Silicon ( IF 3.4 ) Pub Date : 2021-09-10 , DOI: 10.1007/s12633-021-01339-2
Kumari Nibha Priyadarshani 1 , Sangeeta Singh 1 , Kunal Singh 2
Affiliation  

Ge-source dopingless tunnelling field effect transistor (Ge-source DLTFET) with the optimization of dielectric oxide thickness under the source and the gate contacts is proposed and investigated by calibrated 2D TCAD device simulation. As the structure is realized using dopingless technique, this enables lower thermal budget, higher immunity towards the random dopant fluctuations (RDFs) effects and velocity degradation effects. The optimization of dielectric thickness has been done to tune the carrier concentrations induced in source and channel regions in order to improve the device performance. The drive current is magnificently enhanced along with ION/IOFF ratio, peak transconductance and ultra-steep subthreshold slope (SS) is reported for the optimized Si-DLTFET. In addition to this by deploying Ge-source instead of Si source in optimized Si-DLTFET increases ON current slightly and OFF current gets reduced by the order of two as compared to the optimized Si-DLTFET. This improves the ION/IOFF ratio, the reported drive current for Ge-source DLTFET is 5.1 × 10−4 A/μm, along with ION/IOFF ratio as 1.54 × 1013, peak transconductance as 1.26 mS/μm and ultra-steep SS as 1.69 mV/decade. Further, the analog, RF and linearity performance parameters have also been investigated for both the structures and demonstrated notable improvement. The energy efficiency investigation reveals a significant reduction in energy-delay product. Further the linearity analysis is also presented for the reported device structure. This paper indicates the potentials of optimized Si-DLTFET and Ge-source DLTFET as promising candidates for low power analog and RF applications and Ge-source DLTFET has better device dc performance.



中文翻译:

具有增强驱动电流的超陡 Ge 源无掺杂隧道场效应晶体管:直流到线性特性分析

提出并通过校准的 2D TCAD 器件模拟研究了 Ge 源无掺杂隧道场效应晶体管 (Ge 源 DLTFET),该晶体管在源极和栅极触点下优化了电介质氧化物厚度。由于该结构是使用无掺杂技术实现的,因此可以降低热预算,提高对随机掺杂波动 (RDF) 效应和速度退化效应的免疫力。已完成电介质厚度的优化以调整源极和沟道区域中引起的载流子浓度,以提高器件性能。驱动电流随着 I ON /I OFF一起大幅增强报告了优化的 Si-DLTFET 的比率、峰值跨导和超陡亚阈值斜率 (SS)。除此之外,通过在优化的 Si-DLTFET 中部署 Ge 源而不是 Si 源,与优化的 Si-DLTFET 相比,导通电流略有增加,关断电流降低了两个数量级。这提高了 I ON /I OFF比,据报道 Ge 源 DLTFET 的驱动电流为 5.1 × 10 -4 A/μm,I ON /I OFF比为 1.54 × 10 13,峰值跨导为 1.26 mS/μm,超陡 SS 为 1.69 mV/decade。此外,还研究了这两种结构的模拟、RF 和线性性能参数,并证明了显着改进。能效调查显示能量延迟积显着减少。此外,还对报告的器件结构进行了线性分析。本文指出了优化的 Si-DLTFET 和 Ge 源 DLTFET 作为低功率模拟和 RF 应用的有希望的候选者的潜力,Ge 源 DLTFET 具有更好的器件直流性能。

更新日期:2021-09-12
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