Demand for accommodating more and new functionalities within a single chip such as SOC needs novel devices and architecture such as FinFET devices instead of MOSFET. FinFET emerged as a non-planar, multigate device to overcome short channel effects such as subthreshold swing deterioration, drain induced barrier lowering and threshold voltage roll-off which degrade circuit performance. As the need of device technology is mounting in electronic gadgets the important parameters are taken into consideration such as low leakage, high reliability, low power dissipation, and high operating speed. Reliability is one of key considerations in converting a proof of concept into reality. In this work the reliability of FinFET device is studied experimentally according to ITRS (international technology roadmap for semiconductors) roadmap using several standard test protocols such as multiple current stressing, harsher environment conditions, and effect of electromigration. Furthermore, power analysis of FinFET based SRAM is done by using 7 nm BSIM-CMG Predictive technology model files (PTM) in mentor graphics tool. The FinFET based SRAM showed low leakage, low power dissipation, and less delay compared to existing conventional MOSFET based SRAM.

需要在单个芯片（如 SOC）中容纳更多和新功能，需要新的器件和架构，如 FinFET 器件而不是 MOSFET。FinFET 作为一种非平面的多栅器件出现，以克服短沟道效应，例如亚阈值摆动恶化、漏极引起的势垒降低和阈值电压滚降，这会降低电路性能。由于设备技术的需要安装在电子设备中，因此考虑了低泄漏、高可靠性、低功耗和高运行速度等重要参数。可靠性是将概念证明转化为现实的关键考虑因素之一。在这项工作中，根据 ITRS（半导体国际技术路线图）路线图，使用多种标准测试协议，如多电流应力、更恶劣的环境条件和电迁移效应，对 FinFET 器件的可靠性进行了实验研究。此外，通过在导师图形工具中使用 7 nm BSIM-CMG 预测技术模型文件 (PTM) 来完成基于 FinFET 的 SRAM 的功耗分析。与现有的基于 MOSFET 的 SRAM 相比，基于 FinFET 的 SRAM 显示出低泄漏、低功耗和更少的延迟。