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Performance Analysis of Heterojunction and Hetero Dielectric Triple Material Double Gate TFET
Silicon ( IF 3.4 ) Pub Date : 2021-09-08 , DOI: 10.1007/s12633-021-01355-2
C. Sheeja Herobin Rani 1 , S. Edwin Lawrence 1 , R. Solomon Roach 2 , T. S. Arun Samuel 3
Affiliation  

The gate material work function engineering and hetero-dielectric engineering concepts are discussed in this paper to design a novel triple material DG Tunnel FET. The three different work functions and the hetero-dielectric material within the transistor control the charge carrier density in the source, drain, and channel region. The heterojunction germanium and silicon material in the source-channel junction improve tunneling based on the bandgap engineering. The hetero-dielectric materials, namely high–K material in the source region and low-K material in the drain region, suppress the gate-to-drain capacitance effect, enhancing the cut-off frequency. The increased tunneling enhances the ON current, and the tri material restricts the reverse tunneling, which suppresses the ambipolar behaviour of the TFET. The electrical characteristics like surface potential, electric field, drain current, transconductance, and cut-off frequency of the TMDG TFET are simulated using TCAD simulation. Also, results validate the suitable selection of the doping concentration in the source, drain region and different tri-gate work function values for the proposed TMDG TFET. The proposed device shows remarkable progress in ON current of the order (10− 3 A/µm) and the leakage current in Femto range (10− 17 A/µm), with the ION/IOFF current ratio of 1014. The proposed structure is suitable for low-power applications.



中文翻译:

异质结和异质电介质三重材料双栅 TFET 的性能分析

本文讨论了栅极材料功函数工程和异质电介质工程概念,以设计一种新型三重材料 DG 隧道 FET。三种不同的功函数和晶体管内的异质电介质材料控制着源极、漏极和沟道区的电荷载流子密度。源-沟道结中的异质结锗和硅材料基于带隙工程改进了隧道效应。异质电介质材料,即源区的高K材料和漏区的低K材料,抑制了栅漏电容效应,提高了截止频率。增加的隧穿增强了导通电流,而三元材料限制了反向隧穿,从而抑制了 TFET 的双极行为。TMDG TFET 的表面电位、电场、漏电流、跨导和截止频率等电气特性使用 TCAD 模拟进行模拟。此外,结果验证所提出的TMDG TFET的源极,漏区和不同三栅极功函数值中的掺杂浓度的合适选择。所提出的器件在导通电流(10− 3  A/µm) 和毫微微范围内的漏电流 (10 − 17  A/µm),I ON /I OFF电流比为 10 14。所提出的结构适用于低功率应用。

更新日期:2021-09-10
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