Multilevel storage and the continuing scaling down of technology have significantly improved the storage density of phase change memory, but have also brought about a challenge, in that data reliability can degrade due to the resistance drift. To ensure data reliability, many read and write operation technologies have been proposed. However, they only mitigate the influence on data through read and write operations after resistance drift occurs. In this paper, we consider the working principle of multilevel storage for PCM and present a novel 2T2R structure circuit to increase the storage density and reduce the influence of resistance drift fundamentally. To realize 3-bit per cell storage, a wide range of resistances were selected as different states of phase change memory. Then, we proposed a 4:3 compressing encoding scheme to transform the output data into binary data states. Therefore, the designed 2T2R was proven to have optimized storage density and data reliability by monitoring the conductance distribution at four time points (1 ms, 1 s, 6 h, 12 h) in 4000 devices. Simulation results showed that the resistance drift of our proposed 2T2R structure can significantly improve the storage density of multilevel storage and increase the data reliability of phase change memory.

中文翻译：

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使用 2T2R 单元结构增强相变存储器中多级存储的数据可靠性

多级存储和技术的不断缩小显着提高了相变存储器的存储密度，但也带来了挑战，因为电阻漂移会降低数据可靠性。为了保证数据的可靠性，人们提出了很多读写操作技术。然而，它们只是在电阻漂移发生后通过读写操作来减轻对数据的影响。在本文中，我们考虑了PCM多级存储的工作原理，提出了一种新颖的2T2R结构电路，从根本上提高了存储密度，减少了电阻漂移的影响。为了实现每单元 3 位的存储，选择了广泛的电阻作为相变存储器的不同状态。然后，我们提出了一个4：3 压缩编码方案将输出数据转换为二进制数据状态​​。因此，通过监测 4000 台设备中四个时间点（1 ms、1 s、6 h、12 h）的电导分布，证明设计的 2T2R 具有优化的存储密度和数据可靠性。仿真结果表明，我们提出的2T2R结构的电阻漂移可以显着提高多级存储的存储密度，增加相变存储器的数据可靠性。