Two different integration technologies of GaN-on-diamond are explored, direct growth of polycrystalline diamond (PCD) on GaN (sample A) and deposition of GaN on PCD (sample B). The reversed evolution of PCD grain structure is assumed for each technology, resulting in an increasing/decreasing tendency of thermal conductivity with growth thickness. Simulation of AlGaN/GaN high electron mobility transistors on PCD substrate with capped diamond is made considering anisotropic and inhomogeneous thermal conductivities of GaN and PCD, different combinations of thermal boundary resistance (TBR) values at the top diamond/GaN and bottom GaN/PCD substrate are investigated. The results show that the effect of top TBR is limited and increasing the bottom TBR from 6.5 to 100 m²K GW⁻¹ results in a temperature rise of 80.8 C for sample A and 85.3 C for sample B at power dissipation of 10 W mm⁻¹. Enlarging the thickness of capped diamond helps to reduce the junction temperature, which is more effective at small top TBR under constant bottom TBR and at large bottom TBR with fixed top TBR. In addition, increasing gate pitch is a promising solution to reduce junction temperature and a weak dependence of junction temperature on gate width is revealed.

探索了金刚石上 GaN 的两种不同集成技术，在 GaN 上直接生长多晶金刚石 (PCD)（样品 A）和在 PCD 上沉积 GaN（样品 B）。每种技术都假设 PCD 晶粒结构的反向演化，导致热导率随生长厚度增加/减少的趋势。考虑到 GaN 和 PCD 的各向异性和非均匀热导率、顶部金刚石/GaN 和底部 GaN/PCD 衬底的热边界电阻 (TBR) 值的不同组合，在具有封端金刚石的 PCD 衬底上模拟 AlGaN/GaN 高电子迁移率晶体管被调查。结果表明，顶部 TBR 的影响是有限的，将底部 TBR 从 6.5 增加到 100 m ² K GW ^-1结果在80.8℃的温度上升为样品A和以10宽mm的功率耗散85.3℃，样品B ^-1。增加加帽金刚石的厚度有助于降低结温，这在恒定底部 TBR 下的小顶部 TBR 和具有固定顶部 TBR 的大底部 TBR 时更有效。此外，增加栅极间距是降低结温的有前景的解决方案，并且揭示了结温对栅极宽度的弱依赖性。