In this paper, two Phase frequency detector (PFD) architectures and a PFD with lock-in detection (PFD-LID) are proposed that are designed using the new techniques for selectively resetting the outputs to achieve improved average gain with a lower blind zone. The two proposed PFDs are designed and fabricated using 180 nm CMOS process. The circuits are tested with the variations in the supply voltage from 1.3 V to 1.8 V, achieving higher average gain and the measured blind zone of 3 ps, which is around five times less than earlier reported works. Also, the proposed selective reset techniques are used to design the PFD-LID. Both the PFDs and PFD-LID are validated using the traditional phase-locked loop (PLL) architecture by achieving minimal settling time of the PLL.

在本文中，提出了两种相位频率检测器 (PFD) 架构和具有锁定检测功能的 PFD (PFD-LID)，它们使用新技术进行设计，用于选择性地重置输出，以在较低盲区的情况下实现更高的平均增益。这两个提议的 PFD 是使用 180 nm CMOS 工艺设计和制造的。这些电路在 1.3 V 到 1.8 V 的电源电压变化下进行了测试，实现了更高的平均增益和 3 ps 的测量盲区，这比之前报道的工作少了大约五倍。此外，建议的选择性复位技术用于设计 PFD-LID。PFD 和 PFD-LID 均使用传统的锁相环 (PLL) 架构通过实现 PLL 的最短稳定时间进行验证。