With the technology scaling down, the single event transients produced in the combinational circuit lead to an increasing threat to reliability. In this paper, Dummy Gate Enhanced Charge Sharing (DGECS) technique is proposed to mitigate single event transients, and enhances the pulse quenching of logic cells by increasing the charge sharing between key transistors. Mixed-mode 3-D technology computer aided design simulations were carried out with commercial 65nm dual-well CMOS technology. The simulation results show that the proposed layout technique can significantly reduce single event transient pulse widths and even completely quench transient pulses.

中文翻译：

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基于脉冲淬火的单事件瞬态缓解技术

随着技术的缩小，组合电路中产生的单事件瞬态对可靠性的威胁越来越大。在本文中，提出了虚拟栅极增强电荷共享 (DGECS) 技术来减轻单事件瞬态，并通过增加关键晶体管之间的电荷共享来增强逻辑单元的脉冲猝灭。混合模式 3-D 技术计算机辅助设计模拟使用商用 65 纳米双阱 CMOS 技术进行。仿真结果表明，所提出的布局技术可以显着降低单事件瞬态脉冲宽度，甚至可以完全抑制瞬态脉冲。