This paper introduces an FPGA implementation of a pseudo-random number generator (PRNG) using Chen’s chaotic system. This paper mainly focuses on the development of an efficient VLSI architecture of PRNG in terms of bit rate, area resources, latency, maximum length sequence, and randomness. First, we analyze the dynamic behavior of the chaotic trajectories of Chen’s system and set the parameter’s value to maintain low hardware design complexity. A circuit realization of the proposed PRNG is presented using hardwired shifting, additions, subtractions, and multiplexing schemes. The benefit of this architecture, all the binary multiplications (except Xi⋅Yi and Xi⋅Zi) operations are performed using hardwired shifting. Moreover, the generated sequences pass all the 15 statistical tests of NIST, while it generates pseudo-random numbers at a uniform clock rate with minimum hardware complexity. The proposed architecture of PRNG is realized using Verilog HDL, prototyped on the Virtex-5 FPGA (XC5VLX50T) device, and its analysis has been done using the Matlab tool. Performance analysis confirms that the proposed Chen chaotic attractor-based PRNG scheme is simple, secure, and hardware efficient, with high potential to be adopted in cryptography applications.

中文翻译：

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在 FPGA 上使用 Chen 混沌系统的硬件高效伪随机数发生器

本文介绍了使用 Chen 的混沌系统的伪随机数生成器 (PRNG) 的 FPGA 实现。本文主要关注在比特率、区域资源、延迟、最大长度序列和随机性方面开发一种高效的 PRNG VLSI 架构。首先，我们分析了陈氏系统混沌轨迹的动态行为，并设置参数值以保持较低的硬件设计复杂度。提出的 PRNG 的电路实现是使用硬连线移位、加法、减法和多路复用方案提出的。这种架构的好处是，所有的二进制乘法（除了X一世⋅是一世和X一世⋅Z一世)使用硬连线移位执行操作。此外，生成的序列通过了 NIST 的所有 15 项统计测试，同时以统一的时钟速率生成伪随机数，硬件复杂度最低。提出的 PRNG 架构是使用 Verilog HDL 实现的，在 Virtex-5 FPGA (XC5VLX50T) 设备上进行原型设计，并使用 Matlab 工具完成了其分析。性能分析证实，所提出的基于 Chen 混沌吸引子的 PRNG 方案简单、安全、硬件高效，在密码学应用中具有很高的应用潜力。