We use temperature-dependent contact resistivity (ρ_c) measurements to systematically assess the dominant electron transport mechanism in a large set of poly-Si passivating contacts, fabricated by varying (i) the annealing temperature (T_ann), (ii) the oxide thickness (t_ox), (iii) the oxidation method, and (iv) the surface morphology of the Si substrate. The results show that for silicon oxide thicknesses of 1.3–1.5 nm, the dominant transport mechanism changes from tunneling to drift-diffusion via pinholes in the SiO_x layer for increasing T_ann. This transition occurs for T_ann in the range of 850°C-950 °C for a 1.5 nm thick thermal oxide, and 700°C-750 °C for a 1.3 nm thick wet-chemical oxide, which suggests that pinholes appear in wet-chemical oxides after exposure to lower thermal budgets compared to thermal oxides. For SiO_x with t_ox = 2 nm, grown either thermally or by plasma-enhanced atomic layer deposition, carrier transport is pinhole-dominant for T_ann = 1050 °C, whereas no electric current through the SiO_x layer could be detected for lower T_ann. Remarkably, the dominant transport mechanism is not affected by the substrate surface morphology, although lower values of ρ_c were measured on textured wafers compared to planar surfaces. Lifetime measurements suggest that the best carrier selectivity can be achieved by choosing T_ann right above the transition range, but not too high, in order to induce pinhole dominant transport while preserving a good passivation quality.

我们使用与温度相关的接触电阻率 ( ρ _c ) 测量来系统地评估大量多晶硅钝化接触中的主要电子传输机制，通过改变 (i) 退火温度 ( T _ann )，(ii) 氧化物制造厚度 ( t _ox )、(iii) 氧化方法和 (iv) Si 衬底的表面形态。结果表明，对于 1.3-1.5 nm 的氧化硅厚度，主要的传输机制从隧道传输变为漂移扩散，通过 SiO _x层中的针孔来增加T _ann。这种转变发生在T _ann对于 1.5 nm 厚的热氧化物，在 850°C-950 °C 的范围内，对于 1.3 nm 厚的湿化学氧化物，在 700°C-750 °C 的范围内，这表明在暴露于湿化学氧化物后会出现针孔与热氧化物相比具有更低的热预算。对于的SiO _X与吨_牛 = 2nm时，生长的热或通过等离子增强的原子层沉积，载流子传输是针孔显性为Ť_安 = 1050℃，而通过在SiO没有电流_X层可以为下被检测到Ť_安。值得注意的是，主要的传输机制不受基材表面形态的影响，尽管ρ _{c 的}值较低与平面表面相比，在纹理晶片上测量。寿命测量表明，最好的载流子选择性可以通过选择_刚好在过渡范围之上的T _ann来实现，但不要太高，以便在保持良好钝化质量的同时诱导针孔主导传输。