The space environment's hostility requires that the processors used in spacecraft be designed using fault tolerance techniques to reduce the propagation of errors. In this context, this work presents a low-cost fault-tolerant processor based on the RISC-V architecture, an emerging industry standard for building embedded processors. The implemented processor was integrated with a System-on-Chip to assess the cost and efficiency of fault tolerance techniques at the processor and system levels through simulation of fault injection campaigns. The proposed implementation uses physical and information redundancy to reduce the propagation of errors. The processor has a low overhead in silicon compared to other implementations of the same architecture. It mitigates 100% of the single transient faults injected and more than 65% of the transient faults when multiple faults are injected at random moments and locations. The number of errors propagated is slightly higher at the system level because the other system's components are not protected.

太空环境的敌意要求航天器中使用的处理器使用容错技术进行设计，以减少错误的传播。在这种情况下，这项工作提出了一种基于 RISC-V 架构的低成本容错处理器，RISC-V 架构是构建嵌入式处理器的新兴行业标准。实施的处理器与片上系统集成，以通过模拟故障注入活动来评估处理器和系统级别的容错技术的成本和效率。建议的实现使用物理和信息冗余来减少错误的传播。与相同架构的其他实现相比，该处理器在硅片上的开销较低。当在随机时刻和位置注入多个故障时，它可以减轻 100% 的单个瞬态故障注入和 65% 以上的瞬态故障。在系统级别传播的错误数量略高，因为其他系统的组件不受保护。