This paper presents a 12-bit 1 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with foreground calibration for digital-to-analog converter (DAC) mismatch and comparator static offset errors. The proposed foreground calibration utilizes the redundancy to facilitate the detection of DAC weight errors, and compensates for deviations of offset and DAC weights from the ideal value in the analog domain respectively. Benefit from the choice of 0.3 fF unit capacitance, the calibration achieves a 90% reduction in DAC power overhead over the conventional method. The effectiveness of this method is demonstrated by simulations in which differential non-linearity (DNL) is reduced from −1.28 LSB to −0.53 LSB and integral non-linearity (INL) is reduced from 2.20 LSB to 1.08 LSB. The ADC implemented in 40 nm CMOS consumes 3.66 μW from a 1 V supply, and achieves an improved signal-to-noise and distortion ratio (SNDR) of from 59.68 dB to 66.67 dB and a figure of merit (FoM) of 2.07 fJ/conversion-step at Nyquist rate.

本文介绍了一种 12 位 1 MS/s 逐次逼近寄存器 (SAR) 模数转换器 (ADC)，具有针对数模转换器 (DAC) 失配和比较器静态偏移误差的前景校准。所提出的前景校准利用冗余来促进DAC权重误差的检测，并分别补偿偏移和DAC权重与模拟域中理想值的偏差。得益于选择 0.3 fF 单位电容，校准使 DAC 功率开销比传统方法降低了 90%。该方法的有效性通过模拟证明，其中微分非线性 (DNL) 从 -1.28 LSB 降低到 -0.53 LSB，积分非线性 (INL) 从 2.20 LSB 降低到 1.08 LSB。在 40 nm CMOS 中实现的 ADC 消耗 3。