A 56 Gbps 2-tap 4-level pulse amplitude modulation closed-loop decision feedback equalizer (DFE) is designed in 28 nm CMOS technology. The first-tap feedback signal directly tapped from the slicer causes uncontrolled overshoot, resulting in over-correction. With insignificant hardware and power consumption, an overshoot compensation scheme is proposed, which generates an opposite overshoot to compensate the original one. Simulation results show the overshoot caused by different process-voltage-temperature conditions during the sampling aperture is reduced by at least 40%. More than 59% improvement is achieved in recovered eye height over its conventional counterpart with $\ge$ 9 dB channel loss at 14 GHz. In addition, a two-stage slicer is proposed to resolve the critical timing constraints of the first-tap direct feedback path. The receiver occupies an area of 0.19 mm², and consumes a power of 179 mW, achieving 3.2 pJ/bit energy efficiency.

采用 28 nm CMOS 技术设计了 56 Gbps 2-tap 4 级脉冲幅度调制闭环决策反馈均衡器 (DFE)。直接从限幅器抽头的第一抽头反馈信号会导致不受控制的过冲，从而导致过度校正。在硬件和功耗微不足道的情况下，提出了一种过冲补偿方案，它会产生一个相反的过冲来补偿原来的过冲。仿真结果表明，在采样孔径期间由不同的工艺-电压-温度条件引起的过冲至少降低了 40%。与传统对应物相比，恢复的眼高提高了 59% 以上$\ge$14 GHz 时为 9 dB 通道损耗。此外，提出了一种两级切片器来解决第一次直接反馈路径的关键时序约束。接收器占地面积为0.19 mm ²，功耗为179 mW，能效为3.2 pJ/bit。