In this work, the impact of shallow trench isolation (STI) and dual stress liner (DSL) -induced stresses on soft error performance of 30-nm gate length Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET)-based 6T-SRAM cells is studied using process and device simulations. Under nine different stress combinations, i.e., nine different SRAMs, our simulation results show that the stresses introduced from STI and DSL enhance the soft error performance of the cells significantly.

中文翻译：

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应变工程6T-SRAM单元SEU性能的数值研究

在这项工作中，浅沟槽隔离 (STI) 和双应力衬垫 (DSL) 引起的应力对基于 30 nm 栅极长度金属氧化物半导体场效应晶体管 (MOSFET) 的 6T 的软错误性能的影响- SRAM 单元使用工艺和器件仿真进行研究。在九种不同的应力组合下，即九种不同的 SRAM，我们的模拟结果表明，从 STI 和 DSL 引入的应力显着提高了单元的软错误性能。