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An FPGA Based Energy-Efficient Read Mapper With Parallel Filtering and In-Situ Verification
IEEE/ACM Transactions on Computational Biology and Bioinformatics ( IF 4.5 ) Pub Date : 2021-08-20 , DOI: 10.1109/tcbb.2021.3106311
Venkateshwarlu Yellaswamy Gudur 1 , Sidharth Maheshwari 2 , Amit Acharyya 1 , Rishad Shafik 2
Affiliation  

In the assembly pipeline of Whole Genome Sequencing (WGS), read mapping is a widely used method to re-assemble the genome. It employs approximate string matching and dynamic programming-based algorithms on a large volume of data and associated structures, making it a computationally intensive process. Currently, the state-of-the-art data centers for genome sequencing incur substantial setup and energy costs for maintaining hardware, data storage and cooling systems. To enable low-cost genomics, we propose an energy-efficient architectural methodology for read mapping using a single system-on-chip (SoC) platform. The proposed methodology is based on the q-gram lemma and designed using a novel architecture for filtering and verification. The filtering algorithm is designed using a parallel sorted q-gram lemma based method for the first time, and it is complemented by an in-situ verification routine using parallel Myers bit-vector algorithm. We have implemented our design on the Zynq Ultrascale+ XCZU9EG MPSoC platform. It is then extensively validated using real genomic data to demonstrate up to 7.8× energy reduction and up to 13.3× less resource utilization when compared with the state-of-the-art software and hardware approaches.

中文翻译:

具有并行过滤和原位验证的基于 FPGA 的节能读取映射器

在全基因组测序(WGS)的组装流程中,读取映射是一种广泛使用的重新组装基因组的方法。它对大量数据和相关结构采用近似字符串匹配和基于动态编程的算法,使其成为计算密集型过程。目前,最先进的基因组测序数据中心需要大量的设置和能源成本来维护硬件、数据存储和冷却系统。为了实现低成本基因组学,我们提出了一种使用单一片上系统 (SoC) 平台进行读取映射的节能架构方法。所提出的方法基于 q-gram 引理,并使用一种用于过滤和验证的新颖架构进行设计。首次使用基于并行排序的 q-gram 引理的方法设计过滤算法,并辅以使用并行迈尔斯位向量算法的原位验证例程。我们已经在 Zynq Ultrascale+ XCZU9EG MPSoC 平台上实现了我们的设计。然后使用真实的基因组数据对其进行广泛验证,以证明与最先进的软件和硬件方法相比,能量减少高达 7.8 倍,资源利用率降低高达 13.3 倍。
更新日期:2021-08-20
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