In this paper, a 9T SRAM cell with low power (LP9T) and improved performance has been proposed. This cell is free from half-select issue and works with single-ended read and differential write operation in the sub-threshold region. To evaluate the relative performance, the obtained characteristics of LP9T SRAM cell are compared with other state-of-the-art designs at 45-nm technology node. The read and write power dissipation of LP9T SRAM cell is reduced by 1.65× and 1.84× as compared to Conv.6T SRAM cell. In proposed cell, leakage power is reduced by 1.58×, 1.40×, 1.47×, 1.05×, 1.57× and 1.31× as compared to conventional 6T (Conv.6T), low power (LP8T), transmission gate 8T(TG8T), transmission gate 9T (TG9T), Schmitt trigger 9T (ST9T), and positive feedback control 10T (PFC10T) SRAM cells. This reduction in leakage power is attributed to stacking effect. LP9T SRAM cell also exhibits significant improvement in read/write access time as compared to all considered cells. Also, the read and write energy of proposed cell is lowest among all considered cells. The LP9T SRAM cell has 2.2× and 1.63× higher read and write stability as compared to Conv.6T SRAM cell. Proposed SRAM cell has the highest value of ON to OFF current ratio (Ion∕Ioff) which signifies the highest bit-cell density among all considered cells. The LP9T SRAM cell occupies 1.20× large area as compared to Conv.6T SRAM cell. The overall quality of SRAM cell is calculated through the electrical quality metric (EQM). It is observed that LP9T SRAM cell has the highest value of EQM in comparison to considered cells at 0.3V supply voltage.

中文翻译：

---

为超低功耗器件设计具有改进性能的低泄漏 9T SRAM 单元

在本文中，提出了一种具有低功耗 (LP9T) 和改进性能的 9T SRAM 单元。该单元没有半选问题，可在亚阈值区域进行单端读取和差分写入操作。为了评估相对性能，将获得的 LP9T SRAM 单元的特性与 45 纳米技术节点的其他最先进设计进行了比较。LP9T SRAM 单元的读写功耗降低了1.65×和1.84×与 Conv.6T SRAM 单元相比。在建议的电池中，泄漏功率降低了1.58×,1.40×,1.47×,1.05×,1.57×和1.31×与传统的 6T (Conv.6T)、低功耗 (LP8T)、传输门 8T(TG8T)、传输门 9T (TG9T)、施密特触发器 9T (ST9T) 和正反馈控制 10T (PFC10T) SRAM 单元相比。这种泄漏功率的降低归因于堆叠效应。与所有考虑的单元相比，LP9T SRAM 单元在读/写访问时间方面也有显着改善。此外，在所有考虑的单元中，提议的单元的读写能量是最低的。LP9T SRAM 单元具有2.2×和1.63×与 Conv.6T SRAM 单元相比，具有更高的读写稳定性。提出的 SRAM 单元具有最高的 ON 与 OFF 电流比值（一世在∕一世离开) 这表示所有考虑的单元中的最高位单元密度。LP9T SRAM 单元占用1.20×与 Conv.6T SRAM 单元相比，面积更大。SRAM 单元的整体质量通过电气质量指标 (EQM) 计算得出。据观察，与考虑的单元相比，LP9T SRAM 单元的 EQM 值最高，为 0.3V 电源电压。